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    System to improve error code decoding using historical information and associated methods
    3.
    发明授权
    System to improve error code decoding using historical information and associated methods 有权
    系统使用历史信息和相关方法改进错误码解码

    公开(公告)号：US08185801B2

    公开(公告)日：2012-05-22

    申请号：US12023445

    申请日：2008-01-31

    申请人： Timothy J. Dell ,  Luis A. Lastras-Montano ,  Barry M. Trager ,  Shmuel Winograd

    发明人： Timothy J. Dell ,  Luis A. Lastras-Montano ,  Barry M. Trager ,  Shmuel Winograd

    IPC分类号： H03M13/00

    CPC分类号： G06F11/1044

    摘要： A system to improve error code decoding using historical information. An example system includes storage partitioned into memory ranks, and a table to record symbols having failures for each memory rank. The system generates a memory rank score for each memory rank. The system also includes an error control decoder that uses the memory rank score when each memory rank is accessed in order to determine whether an error should be corrected or not.

    摘要翻译： 一种使用历史信息改进错误代码解码的系统。 示例性系统包括分割成存储器排名的存储器，以及用于记录具有每个存储器级别的故障的符号的表。 系统为每个存储器级别生成内存等级分数。 该系统还包括错误控制解码器，当访问每个存储器等级时，使用存储器等级分数，以便确定是否应该纠正错误。

    System to Improve Memory Reliability and Associated Methods
    4.
    发明申请
    System to Improve Memory Reliability and Associated Methods 有权
    提高内存可靠性和相关方法的系统

    公开(公告)号：US20100287445A1

    公开(公告)日：2010-11-11

    申请号：US12023374

    申请日：2008-01-31

    申请人： Timothy J. Dell ,  Luis A. Lastras-Montano ,  Barry M. Trager ,  Shmuel Winograd

    发明人： Timothy J. Dell ,  Luis A. Lastras-Montano ,  Barry M. Trager ,  Shmuel Winograd

    IPC分类号： H03M13/05 ,  G06F11/10 ,  H03M13/07

    CPC分类号： H03M13/1545 ,  G06F11/1044 ,  H03M13/1515

    摘要： A system to improve memory reliability in computer systems that may include memory chips, and may rely on a error control encoder to send codeword symbols for storage in each of the memory chips. At least two symbols from a codeword are assigned to each memory chip and therefore failure of any of the memory chips could affect two symbols or more. The system may also include a table to record failures and partial failures of the codeword symbols for each of the memory chips so the error control encoder can correct subsequent partial failures based upon the previous partial failures. The error control coder is capable of correcting and/or detecting more errors if only a fraction of a chip is noted in the table as having a failure as opposed to a full chip noted as having a failure.

    摘要翻译： 一种用于提高可能包括存储器芯片的计算机系统中的存储器可靠性的系统，并且可以依赖于错误控制编码器来发送用于存储在每个存储器芯片中的码字符号。 来自码字的至少两个符号被分配给每个存储器芯片，因此任何存储器芯片的故障可能影响两个或更多个符号。 该系统还可以包括用于记录每个存储器芯片的码字符号的故障和部分故障的表，因此错误控制编码器可以基于先前的部分故障来校正随后的部分故障。 误差控制编码器能够校正和/或检测更多的误差，如果在表中只有一部分芯片被注意为具有故障，而不是被称为具有故障的全芯片。

    System to Improve Error Code Decoding Using Historical Information and Associated Methods
    5.
    发明申请
    System to Improve Error Code Decoding Using Historical Information and Associated Methods 有权
    使用历史信息和相关方法改进错误代码解码的系统

    公开(公告)号：US20100287454A1

    公开(公告)日：2010-11-11

    申请号：US12023445

    申请日：2008-01-31

    申请人： Timothy J. Dell ,  Luis A. Lastras-Montano ,  Barry M. Trager ,  Shmuel Winograd

    发明人： Timothy J. Dell ,  Luis A. Lastras-Montano ,  Barry M. Trager ,  Shmuel Winograd

    IPC分类号： H03M13/09 ,  G06F11/10

    CPC分类号： G06F11/1044

    摘要： A system to improve error code decoding using historical information may include storage partitioned into memory ranks, and a table to record symbols having failures for each memory rank. The system may also generate a memory rank score for each memory rank. The system may also include an error control decoder that may use the memory rank score when each memory rank is accessed in order to determine whether an error should be corrected or not.

    摘要翻译： 使用历史信息改进错误代码解码的系统可以包括分割成存储器排名的存储器，以及记录具有每个存储器级别故障的符号的表。 系统还可以为每个存储器等级产生存储器等级分数。 系统还可以包括错误控制解码器，其可以在访问每个存储器级时使用存储器等级分数，以便确定是否应该纠正错误。

    System to improve memory reliability and associated methods
    6.
    发明授权
    System to improve memory reliability and associated methods 有权
    系统提高内存可靠性和相关方法

    公开(公告)号：US08171377B2

    公开(公告)日：2012-05-01

    申请号：US12023374

    申请日：2008-01-31

    申请人： Timothy J. Dell ,  Luis A. Lastras-Montano ,  Barry M. Trager ,  Shmuel Winograd

    发明人： Timothy J. Dell ,  Luis A. Lastras-Montano ,  Barry M. Trager ,  Shmuel Winograd

    IPC分类号： G11C29/00

    CPC分类号： H03M13/1545 ,  G06F11/1044 ,  H03M13/1515

    摘要： A system to improve memory reliability in computer systems that may include memory chips, and may rely on a error control encoder to send codeword symbols for storage in each of the memory chips. At least two symbols from a codeword are assigned to each memory chip and therefore failure of any of the memory chips could affect two symbols or more. The system may also include a table to record failures and partial failures of the codeword symbols for each of the memory chips so the error control encoder can correct subsequent partial failures based upon the previous partial failures. The error control coder is capable of correcting and/or detecting more errors if only a fraction of a chip is noted in the table as having a failure as opposed to a full chip noted as having a failure.

    摘要翻译： 一种用于提高可能包括存储器芯片的计算机系统中的存储器可靠性的系统，并且可以依赖于错误控制编码器来发送用于存储在每个存储器芯片中的码字符号。 来自码字的至少两个符号被分配给每个存储器芯片，因此任何存储器芯片的故障可能影响两个或更多个符号。 该系统还可以包括用于记录每个存储器芯片的码字符号的故障和部分故障的表，因此错误控制编码器可以基于先前的部分故障来校正随后的部分故障。 误差控制编码器能够校正和/或检测更多的误差，如果在表中只有一部分芯片被注意为具有故障，而不是被称为具有故障的全芯片。

    Cascade interconnect memory system with enhanced reliability
    7.
    发明授权
    Cascade interconnect memory system with enhanced reliability 有权
    级联互连存储器系统具有增强的可靠性

    公开(公告)号：US08245105B2

    公开(公告)日：2012-08-14

    申请号：US12166235

    申请日：2008-07-01

    申请人： Timothy J. Dell ,  Kevin C. Gower ,  Warren E. Maule ,  Michael R. Trombley

    发明人： Timothy J. Dell ,  Kevin C. Gower ,  Warren E. Maule ,  Michael R. Trombley

    IPC分类号： H03M13/00

    CPC分类号： G06F11/0772 ,  G06F11/073 ,  G06F11/0781 ,  G06F11/1004 ,  G11C5/04 ,  G11C29/70 ,  G11C2029/0409 ,  G11C2029/0411

    摘要： A hub device, memory system, and method for providing a cascade interconnect memory system with enhanced reliability. The hub device includes an interface to a high-speed bus for communicating with a memory controller. The memory controller and the hub device are included in a cascade interconnect memory system and the high-speed bus includes bit lanes and one or more clock lanes. The hub device also includes a bi-directional fault signal line in communication with the memory controller and readable by a service interface. The hub device also includes a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures. In addition, the hub device includes error recovery logic for responding to a failure detected at the hub device.

    摘要翻译： 一种用于提供具有增强的可靠性的级联互连存储器系统的集线器设备，存储器系统和方法。 集线器设备包括与高速总线的接口，用于与存储器控制器进行通信。 存储器控制器和集线器设备包括在级联互连存储器系统中，并且高速总线包括位通道和一个或多个时钟通道。 集线器设备还包括与存储器控制器通信并可由服务接口读取的双向故障信号线。 集线器设备还包括用于存储关于在集线器设备处检测到的故障的信息的故障隔离寄存器（FIR），该信息包括检测到的故障的严重性级别。 此外，集线器设备包括用于响应在集线器设备处检测到的故障的错误恢复逻辑。

    CASCADE INTERCONNECT MEMORY SYSTEM WITH ENHANCED RELIABILITY
    8.
    发明申请
    CASCADE INTERCONNECT MEMORY SYSTEM WITH ENHANCED RELIABILITY 有权
    具有增强可靠性的CASCADE互连存储器系统

    公开(公告)号：US20100005366A1

    公开(公告)日：2010-01-07

    申请号：US12166235

    申请日：2008-07-01

    申请人： Timothy J. Dell ,  Kevin C. Gower ,  Warren E. Maule ,  Michael R. Trombley

    发明人： Timothy J. Dell ,  Kevin C. Gower ,  Warren E. Maule ,  Michael R. Trombley

    IPC分类号： G06F11/10 ,  H03M13/00 ,  G11C29/00 ,  G06F11/14

    CPC分类号： G06F11/0772 ,  G06F11/073 ,  G06F11/0781 ,  G06F11/1004 ,  G11C5/04 ,  G11C29/70 ,  G11C2029/0409 ,  G11C2029/0411

    摘要： A hub device, memory system, and method for providing a cascade interconnect memory system with enhanced reliability. The hub device includes an interface to a high-speed bus for communicating with a memory controller. The memory controller and the hub device are included in a cascade interconnect memory system and the high-speed bus includes bit lanes and one or more clock lanes. The hub device also includes a bi-directional fault signal line in communication with the memory controller and readable by a service interface. The hub device also includes a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures. In addition, the hub device includes error recovery logic for responding to a failure detected at the hub device. Responding to the error includes recording a severity level of the failure in the FIR and taking an action at the hub device that is responsive to the severity level of the failure. The action includes one or more of fast clock stop, setting the bi-directional fault indicator, setting cyclical redundancy code (CRC) bits and transmitting them to the memory controller, re-try, sparing out a bit lane and sparing out a clock lane.

    摘要翻译： 一种用于提供具有增强的可靠性的级联互连存储器系统的集线器设备，存储器系统和方法。 集线器设备包括与高速总线的接口，用于与存储器控制器进行通信。 存储器控制器和集线器设备包括在级联互连存储器系统中，并且高速总线包括位通道和一个或多个时钟通道。 集线器设备还包括与存储器控制器通信并可由服务接口读取的双向故障信号线。 集线器设备还包括用于存储关于在集线器设备处检测到的故障的信息的故障隔离寄存器（FIR），该信息包括检测到的故障的严重性级别。 此外，集线器设备包括用于响应在集线器设备处检测到的故障的错误恢复逻辑。 响应该错误包括在FIR中记录故障的严重性级别，并在响应于故障严重性级别的集线器设备上执行操作。 该动作包括一个或多个快速时钟停止，设置双向故障指示器，设置循环冗余码（CRC）位并将其发送到存储器控制器，重新尝试，省略一个位线并省出一个时钟通道 。