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    CORRECTING MEMORY DEVICE AND MEMORY CHANNEL FAILURES IN THE PRESENCE OF KNOWN MEMORY DEVICE FAILURES
    3.
    发明申请
    CORRECTING MEMORY DEVICE AND MEMORY CHANNEL FAILURES IN THE PRESENCE OF KNOWN MEMORY DEVICE FAILURES 失效
    在存在的存储器件故障存在的情况下修正存储器件和存储器通道故障

    公开(公告)号：US20120198309A1

    公开(公告)日：2012-08-02

    申请号：US13016977

    申请日：2011-01-29

    申请人： Luiz C. Alves ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens ,  Barry M. Trager

    发明人： Luiz C. Alves ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens ,  Barry M. Trager

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： G06F11/10 ,  H03M13/13 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19

    摘要： Correcting memory device (chip) and memory channel failures in the presence of known memory device failures. A memory channel failure is located and corrected, or alternatively up to c chip failures are corrected and up to d chip failures are detected in the presence of up to u chips that are marked as suspect. A first stage of decoding is performed that results in recovering an estimate of correctable errors affecting the data or in declaring an uncorrectable error state. When an uncorrectable error state is declared, a second stage of decoding is performed to attempt to correct u erasures and a channel error in M iterations where the channel location is changed in each iteration. A correctable error is declared in response to exactly one of the M iterations being successful.

    摘要翻译： 在存在已知存储器件故障的情况下更正存储器件（芯片）和存储器通道故障。 存储器通道故障被定位和校正，或者高达c个芯片故障被校正，并且在存在被标记为可疑的最多u个芯片的情况下，检测到高达d个芯片故障。 执行解码的第一阶段，其导致恢复影响数据的可校正错误的估计或者宣告不可校正的错误状态。 当声明不可校正的错误状态时，执行第二级解码以尝试在每次迭代中改变通道位置的M次迭代中纠正擦除和通道错误。 响应正好一个M次迭代成功声明可纠正的错误。

    ERROR CORRECTION AND DETECTION IN A REDUNDANT MEMORY SYSTEM
    4.
    发明申请
    ERROR CORRECTION AND DETECTION IN A REDUNDANT MEMORY SYSTEM 有权
    冗余存储系统中的错误校正和检测

    公开(公告)号：US20110320914A1

    公开(公告)日：2011-12-29

    申请号：US12822503

    申请日：2010-06-24

    申请人： Luiz C. Alves ,  Kevin C. Gower ,  Lisa C. Gower ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens

    发明人： Luiz C. Alves ,  Kevin C. Gower ,  Lisa C. Gower ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens

    IPC分类号： G06F11/10

    CPC分类号： G06F11/1004 ,  G06F11/108

    摘要： Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including a plurality of memory devices; a cyclical redundancy code (CRC) mechanism for detecting that one of the memory channels has failed, and for marking the memory channel as a failing memory channel; and an error correction code (ECC) mechanism. The ECC is configured for ignoring the marked memory channel and for detecting and correcting additional memory device failures on memory devices located on one or more of the other memory channels, thereby allowing the memory system to continue to run unimpaired in the presence of the memory channel failure.

    摘要翻译： 在包括存储器控制器的冗余存储器系统中的错误校正和检测; 与存储器控制器通信的多个存储器通道，存储器通道包括多个存储器件; 用于检测存储器通道之一的循环冗余码（CRC）机制已经失败，并用于将存储器通道标记为故障存储器通道; 和纠错码（ECC）机制。 ECC被配置为忽略标记的存储器通道并且用于检测和校正位于一个或多个其它存储器通道上的存储器设备上的附加存储器件故障，从而允许存储器系统在存在存储器通道的情况下继续运行不受损害 失败。

    Method, system and storage medium for redundant input/output access
    6.
    发明授权
    Method, system and storage medium for redundant input/output access 有权
    用于冗余输入/输出访问的方法，系统和存储介质

    公开(公告)号：US07656789B2

    公开(公告)日：2010-02-02

    申请号：US11092033

    申请日：2005-03-29

    申请人： Luiz C. Alves ,  Daniel F. Casper ,  Steven G. Glassen ,  Daniel J. Stigliani, Jr.

    发明人： Luiz C. Alves ,  Daniel F. Casper ,  Steven G. Glassen ,  Daniel J. Stigliani, Jr.

    IPC分类号： H04L12/26

    CPC分类号： H04L1/22

    摘要： A system, method and storage medium for providing redundant I/O access between a plurality of interconnected processor nodes and I/O resources. The method includes determining whether a primary path between the interconnected processor nodes and the I/O resources is operational, where the primary path includes a first processor node and a primary multiplexer. If the primary path is operational, the transactions are routed via the primary path. If the primary path is not operational, the transactions are routed between the interconnected processor nodes and the I/O resources via an alternate path that includes a second processor node and an alternate multiplexer.

    摘要翻译： 一种用于在多个互连的处理器节点和I / O资源之间提供冗余I / O访问的系统，方法和存储介质。 该方法包括确定互连处理器节点和I / O资源之间的主路径是否可操作，其中主路径包括第一处理器节点和主多路复用器。 如果主路径可操作，则通过主路径路由事务。 如果主路径不可操作，则经由包括第二处理器节点和替代多路复用器的备用路径在互连的处理器节点和I / O资源之间路由事务。

    RAIM system using decoding of virtual ECC
    8.
    发明授权
    RAIM system using decoding of virtual ECC 有权
    RAIM系统使用虚拟ECC的解码

    公开(公告)号：US08549378B2

    公开(公告)日：2013-10-01

    申请号：US12822469

    申请日：2010-06-24

    申请人： Luiz C. Alves ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens ,  Barry M. Trager

    发明人： Luiz C. Alves ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens ,  Barry M. Trager

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1044 ,  G06F11/108 ,  H03M13/19 ,  H03M13/2906 ,  H03M13/3761

    摘要： Error correction and detection in a redundant memory system including a a computer implemented method that includes receiving data including error correction code (ECC) bits, the receiving from a plurality of channels, each channel comprising a plurality of memory devices at memory device locations. The method also includes computing syndromes of the data; receiving a channel identifier of one of the channels; and removing a contribution of data received on the channel from the computed syndromes, the removing resulting in channel adjusted syndromes. The channel adjusted syndromes are decoded resulting in channel adjusted memory device locations of failing memory devices, the channel adjusted memory device locations corresponding to memory device locations.

    摘要翻译： 在包括计算机实现的方法的冗余存储器系统中的错误校正和检测，所述方法包括接收包括纠错码（ECC）位的数据，从多个信道接收每个信道包括存储器设备位置处的多个存储器件。 该方法还包括计算数据的综合征; 接收一个频道的频道标识符; 以及从所计算的综合征中去除在所述信道上接收的数据的贡献，所述移除导致频道调整的综合征。 频道调整后的综合征被解码，导致故障存储器件的通道调整的存储器件位置，对应于存储器件位置的通道调整的存储器件位置。

    Correcting memory device and memory channel failures in the presence of known memory device failures
    9.
    发明授权
    Correcting memory device and memory channel failures in the presence of known memory device failures 失效
    在存在已知存储器件故障的情况下更正存储器件和存储器通道故障

    公开(公告)号：US08522122B2

    公开(公告)日：2013-08-27

    申请号：US13016977

    申请日：2011-01-29

    申请人： Luiz C. Alves ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens ,  Barry M. Trager

    发明人： Luiz C. Alves ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens ,  Barry M. Trager

    IPC分类号： H03M13/00

    CPC分类号： G06F11/10 ,  H03M13/13 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19

    摘要： Correcting memory device (chip) and memory channel failures in the presence of known memory device failures. A memory channel failure is located and corrected, or alternatively up to c chip failures are corrected and up to d chip failures are detected in the presence of up to u chips that are marked as suspect. A first stage of decoding is performed that results in recovering an estimate of correctable errors affecting the data or in declaring an uncorrectable error state. When an uncorrectable error state is declared, a second stage of decoding is performed to attempt to correct u erasures and a channel error in M iterations where the channel location is changed in each iteration. A correctable error is declared in response to exactly one of the M iterations being successful.

    摘要翻译： 在存在已知存储器件故障的情况下更正存储器件（芯片）和存储器通道故障。 存储器通道故障被定位和校正，或者高达c个芯片故障被校正，并且在存在被标记为可疑的最多u个芯片的情况下，检测到高达d个芯片故障。 执行解码的第一阶段，其导致恢复影响数据的可校正错误的估计或者宣告不可校正的错误状态。 当声明不可校正的错误状态时，执行第二级解码以尝试在每次迭代中改变通道位置的M次迭代中纠正擦除和通道错误。 响应正好一个M次迭代成功声明可纠正的错误。

    Error correction and detection in a redundant memory system
    10.
    发明授权
    Error correction and detection in a redundant memory system 有权
    冗余存储器系统中的错误校正和检测

    公开(公告)号：US08484529B2

    公开(公告)日：2013-07-09

    申请号：US12822503

    申请日：2010-06-24

    申请人： Luiz C. Alves ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens ,  Lisa C. Gower

    发明人： Luiz C. Alves ,  Kevin C. Gower ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1004 ,  G06F11/108

    摘要： Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including a plurality of memory devices; a cyclical redundancy code (CRC) mechanism for detecting that one of the memory channels has failed, and for marking the memory channel as a failing memory channel; and an error correction code (ECC) mechanism. The ECC is configured for ignoring the marked memory channel and for detecting and correcting additional memory device failures on memory devices located on one or more of the other memory channels, thereby allowing the memory system to continue to run unimpaired in the presence of the memory channel failure.

    摘要翻译： 在包括存储器控制器的冗余存储器系统中的错误校正和检测; 与存储器控制器通信的多个存储器通道，存储器通道包括多个存储器件; 用于检测存储器通道之一的循环冗余码（CRC）机制已经失败，并用于将存储器通道标记为故障存储器通道; 和纠错码（ECC）机制。 ECC被配置为忽略标记的存储器通道并且用于检测和校正位于一个或多个其它存储器通道上的存储器设备上的附加存储器件故障，从而允许存储器系统在存在存储器通道的情况下继续运行不受损害 失败。