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1.发明申请METHOD FOR SCALABLE DERIVATION OF AN IMPLICATION-BASED REACHABLE STATE SET OVERAPPROXIMATION 失效基于影响的可达到状态的可扩展派生方法设置过度预测公开(公告)号：US20100185993A1
公开(公告)日：2010-07-22
申请号：US12357907
申请日：2009-01-22
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method, system and computer program product for integrating implication-based analysis and equivalent gate analysis to maintain transitive reduction in an implication graph over a sequence of graph operations. One or more gates of a design are identified that are equivalent in all reachable states. Equivalent gates are assigned to an equivalence class when all gates within the equivalence class are equal. During the implication-based analysis the system determines when one or more implication paths are associated with the one or more equivalence classes, and an implication is generated at the implication path associated with the equivalence classes. A transitively reduced graph is received depicting the implications and equivalence classes of the design. When one or more operations are assigned to the transitively reduced graph, the graph is automatically adjusted to maintain transitive reduction.
摘要翻译： 一种方法，系统和计算机程序产品，用于整合基于影响的分析和等效门分析，以维持图形操作序列中的含义图形的传递性减少。 识别出在所有可达状态下等效的设计的一个或多个门。 当等价类中的所有门相等时，将等效门分配给等价类。 在基于暗示的分析中，系统确定何时一个或多个含义路径与一个或多个等价类相关联，并且在与等价类相关联的隐含路径上生成含义。 接收到一个过渡缩减的图形，描述了设计的含义和等价类。 当将一个或多个操作分配给转移缩减图时，会自动调整图表以维持传递减少。
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2.发明申请Techniques for Employing Retiming and Transient Simplification on Netlists That Include Memory Arrays 失效对包含内存数组的网络表进行重定时和瞬态简化的技术公开(公告)号：US20120054702A1
公开(公告)日：2012-03-01
申请号：US12872490
申请日：2010-08-31
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A technique for performing an analysis of a logic design (that includes a native memory array embodied in a netlist) includes detecting an initial transient behavior in the logic design as embodied in the netlist. The technique also includes determining a duration of the initial transient behavior and gathering reduction information on the logic design based on the initial transient behavior. The netlist is then modified based on the reduction information.
摘要翻译： 用于执行对逻辑设计（包括在网表中包含的本地存储器阵列）的分析的技术包括检测在网表中体现的逻辑设计中的初始瞬态行为。 该技术还包括基于初始瞬态行为来确定初始瞬态行为的持续时间并收集关于逻辑设计的减少信息。 然后基于减少信息来修改网表。
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3.发明申请METHOD AND SYSTEM FOR SCALABLE REDUCTION IN REGISTERS WITH SAT-BASED RESUBSTITUTION 失效用于基于SAT的调整的寄存器中可缩放的方法和系统公开(公告)号：US20120167024A1
公开(公告)日：2012-06-28
申请号：US13415924
申请日：2012-03-09
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method, system, and computer program product for reducing the size of a logic network design, prior to verification of the logic network design. The method includes eliminating registers to reduce the size of the logic network design; thereby, increasing the speed and functionality of the verification process, and decreasing the size of the logic network design. The system identifies one or more compatible resubstitutions of a selected register, wherein the compatible resubstitution expresses the selected register as one or more pre-existing registers of fixed initial state. The resubstitutions are refined utilizing design invariants. When one more resubstitutions are preformed, the system eliminates the selected registers to reduce the size of the logic network design. As a result of the resubstitution process, a logic network design of reduced size is generated.
摘要翻译： 在验证逻辑网络设计之前，用于减小逻辑网络设计大小的方法，系统和计算机程序产品。 该方法包括消除寄存器以减小逻辑网络设计的大小; 从而增加验证过程的速度和功能，并减小逻辑网络设计的大小。 系统识别所选择的寄存器的一个或多个兼容的重新配置，其中兼容重新配置将所选择的寄存器表示为一个或多个预先存在的固定初始状态的寄存器。 利用设计不变量来改进重组。 当再进行一次重新配置时，系统将删除所选择的寄存器以减小逻辑网络设计的大小。 作为重新配置处理的结果，生成尺寸减小的逻辑网络设计。
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4.发明申请公开(公告)号：US20100293513A1
公开(公告)日：2010-11-18
申请号：US12467097
申请日：2009-05-15
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Methods and systems are provided for reducing an original circuit design into a simplified circuit design by merging gates that may not be equivalent but can be demonstrated to preserve target assertability with respect to the original circuitry design. A composite netlist is created from the simplified netlist and the original netlist. The composite netlist includes a number of targets that imply the existence of a target in the simplified netlist and a corresponding target in the original netlist. The implications are verified and then validated to ensure the simplied circuit design is a suitable replacement for the original circuit design.
摘要翻译： 提供了方法和系统，用于通过合并可能不相等但可被证明能够保持目标可靠性的原始电路设计的门来将原始电路设计减少为简化的电路设计。 复合网表由简化网表和原网表创建。 复合网表包括许多目标，这些目标意味着简化网表中存在目标，而在原始网表中存在相应的目标。 这些含义经过验证，然后被验证，以确保简化的电路设计是原始电路设计的合适替代品。
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