-
1.发明申请Techniques for Employing Retiming and Transient Simplification on Netlists That Include Memory Arrays 失效对包含内存数组的网络表进行重定时和瞬态简化的技术公开(公告)号：US20120054702A1
公开(公告)日：2012-03-01
申请号：US12872490
申请日：2010-08-31
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A technique for performing an analysis of a logic design (that includes a native memory array embodied in a netlist) includes detecting an initial transient behavior in the logic design as embodied in the netlist. The technique also includes determining a duration of the initial transient behavior and gathering reduction information on the logic design based on the initial transient behavior. The netlist is then modified based on the reduction information.
摘要翻译： 用于执行对逻辑设计（包括在网表中包含的本地存储器阵列）的分析的技术包括检测在网表中体现的逻辑设计中的初始瞬态行为。 该技术还包括基于初始瞬态行为来确定初始瞬态行为的持续时间并收集关于逻辑设计的减少信息。 然后基于减少信息来修改网表。
-
2.发明申请METHOD, SYSTEM AND APPLICATION FOR SEQUENTIAL COFACTOR-BASED ANALYSIS OF NETLISTS 有权方法，系统和应用程序，用于基于网格的基于配置因子的分析公开(公告)号：US20100251197A1
公开(公告)日：2010-09-30
申请号：US12410962
申请日：2009-03-25
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Methods, systems and computer products are provided for reducing the design size of an integrated circuit while preserving the behavior of the design with respect to verification results. A multiplexer is inserted at the gate being analyzed, and the multiplexer selector is controlled to provide a predetermined output for one frame at the point being analyzed. It is then determined whether the circuit remains equivalent during application of the predetermined output in order to decide whether the gate being analyzed is a candidate for replacement.
摘要翻译： 提供了方法，系统和计算机产品，用于减少集成电路的设计尺寸，同时保持设计相对于验证结果的行为。 在被分析的门处插入复用器，并且多路复用器选择器被控制以在被分析的点处为一帧提供预定的输出。 然后在应用预定输出期间确定电路是否保持等效，以便确定被分析的门是否是替换候选。
-
3.发明申请METHOD FOR SCALABLE DERIVATION OF AN IMPLICATION-BASED REACHABLE STATE SET OVERAPPROXIMATION 失效基于影响的可达到状态的可扩展派生方法设置过度预测公开(公告)号：US20100185993A1
公开(公告)日：2010-07-22
申请号：US12357907
申请日：2009-01-22
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method, system and computer program product for integrating implication-based analysis and equivalent gate analysis to maintain transitive reduction in an implication graph over a sequence of graph operations. One or more gates of a design are identified that are equivalent in all reachable states. Equivalent gates are assigned to an equivalence class when all gates within the equivalence class are equal. During the implication-based analysis the system determines when one or more implication paths are associated with the one or more equivalence classes, and an implication is generated at the implication path associated with the equivalence classes. A transitively reduced graph is received depicting the implications and equivalence classes of the design. When one or more operations are assigned to the transitively reduced graph, the graph is automatically adjusted to maintain transitive reduction.
摘要翻译： 一种方法，系统和计算机程序产品，用于整合基于影响的分析和等效门分析，以维持图形操作序列中的含义图形的传递性减少。 识别出在所有可达状态下等效的设计的一个或多个门。 当等价类中的所有门相等时，将等效门分配给等价类。 在基于暗示的分析中，系统确定何时一个或多个含义路径与一个或多个等价类相关联，并且在与等价类相关联的隐含路径上生成含义。 接收到一个过渡缩减的图形，描述了设计的含义和等价类。 当将一个或多个操作分配给转移缩减图时，会自动调整图表以维持传递减少。
-
4.发明申请METHOD AND SYSTEM FOR SCALABLE REDUCTION IN REGISTERS WITH SAT-BASED RESUBSTITUTION 失效用于基于SAT的调整的寄存器中可缩放的方法和系统公开(公告)号：US20120167024A1
公开(公告)日：2012-06-28
申请号：US13415924
申请日：2012-03-09
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method, system, and computer program product for reducing the size of a logic network design, prior to verification of the logic network design. The method includes eliminating registers to reduce the size of the logic network design; thereby, increasing the speed and functionality of the verification process, and decreasing the size of the logic network design. The system identifies one or more compatible resubstitutions of a selected register, wherein the compatible resubstitution expresses the selected register as one or more pre-existing registers of fixed initial state. The resubstitutions are refined utilizing design invariants. When one more resubstitutions are preformed, the system eliminates the selected registers to reduce the size of the logic network design. As a result of the resubstitution process, a logic network design of reduced size is generated.
摘要翻译： 在验证逻辑网络设计之前，用于减小逻辑网络设计大小的方法，系统和计算机程序产品。 该方法包括消除寄存器以减小逻辑网络设计的大小; 从而增加验证过程的速度和功能，并减小逻辑网络设计的大小。 系统识别所选择的寄存器的一个或多个兼容的重新配置，其中兼容重新配置将所选择的寄存器表示为一个或多个预先存在的固定初始状态的寄存器。 利用设计不变量来改进重组。 当再进行一次重新配置时，系统将删除所选择的寄存器以减小逻辑网络设计的大小。 作为重新配置处理的结果，生成尺寸减小的逻辑网络设计。
-
公开(公告)号：US20080228694A1
公开(公告)日：2008-09-18
申请号：US12129976
申请日：2008-05-30
IPC分类号： G06F17/30
CPC分类号： G06F17/504
摘要： A method for performing verification includes selecting a first set containing a seed register and adding to a second set a result of a subtraction of a fanout of the first set from a fanin of the first set. A third set is rendered equal to a result of a subtraction of a fanin of the second set from a fanout of the second set, and whether a combination of the first set and the third set is equivalent to the first set is determined. In response to determining that the combination of the first set and the second set is not equivalent to the first set, a min-cut of the first set and the second set containing a minimal set of predicates between a first component and the logic to which the component fans out, wherein the logic is bordered by the second set is returned.
摘要翻译： 一种用于执行验证的方法包括：选择包含种子寄存器的第一集合，并且从第一组的扇区中减去第一组的扇出结果，向第二组添加结果。 第三组被赋予等于从第二组的扇出中减去第二组的扇形的结果，以及第一组和第三组的组合是否等同于第一组的结果。 响应于确定第一集合和第二集合的组合不等同于第一集合，第一集合和第二集合的最小化包含第一组件和逻辑之间的最小一组谓词 组件风扇出来，其中返回逻辑与第二组相邻的逻辑。
-
-
-
-
搜索结果
5 条记录 (耗时 0.016 秒)
