公开(公告)号：US20240369624A1

公开(公告)日：2024-11-07

申请号：US18287141

申请日：2022-04-12

Applicant: JENOPTIK Optical Systems GmbH

Inventor： Christian KARRAS ,  Tobias GNAUSCH ,  Robert BUETTNER ,  Kay REETZ ,  Armin GRUNDMANN ,  Thomas KADEN

IPC: G01R31/28 ,  G01R31/311

Abstract: A method for testing optoelectronic chips that are arranged on a wafer and comprise electric interfaces in the form of contact pads and optical interfaces, which are arranged in a fixed manner relative to the electric interfaces, in the form of optical deflecting elements, e.g. grating couplers, at a specified coupling angle. In the process, the wafer is adjusted in three adjustment steps in such a manner that one of the chips is positioned relative to a contacting module such that the electric interfaces of the chip and the contacting module are in contact with one another and the optical interfaces of the chip and the contacting module assume a maximum position of the optical coupling.