公开(公告)号：US20160105188A1

公开(公告)日：2016-04-14

申请号：US14837731

申请日：2015-08-27

Applicant: JONG-PIL CHO ,  YOUNG-JOO LEE

Inventor： JONG-PIL CHO ,  YOUNG-JOO LEE

IPC: H03L7/087 ,  H04L7/00 ,  H04B5/00 ,  H04L7/033 ,  H03L7/089 ,  H03L7/099

CPC classification number: H03L7/087 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/18 ,  H03L7/23 ,  H04B5/0025 ,  H04B5/0031 ,  H04B5/0056 ,  H04L7/0008

Abstract: A semiconductor device including a PLL providing candidate clocks of different phases in response to a first clock received from a reader via an antenna, a phase difference detector detecting a phase difference between the first clock and a clock from the candidate clocks, a phase difference controller that selects another clock from the candidate clocks, and a driver that provides transmission data synchronously with the another clock to the reader.

Abstract translation: 一种半导体器件，包括响应于从读取器经由天线接收的第一时钟，提供不同相位的候选时钟的PLL;相位差检测器，检测来自候选时钟的第一时钟和时钟之间的相位差;相位差控制器 从候选时钟中选择另一个时钟，以及向读取器提供与另一时钟同步的传输数据的驱动器。