-
1.再颁专利Systems and methods for implementing a sample rate converter using hardware and software to maximize speed and flexibility 有权使用硬件和软件实现采样率转换器的系统和方法，以最大限度地提高速度和灵活性公开(公告)号：USRE43489E1
公开(公告)日：2012-06-26
申请号：US12359021
申请日：2009-01-23
申请人： Jack B. Andersen , Larry E. Hand , Daniel L. W. Chieng , Joel W. Page , Wilson E. Taylor , Tonya Andersen
发明人： Jack B. Andersen , Larry E. Hand , Daniel L. W. Chieng , Joel W. Page , Wilson E. Taylor , Tonya Andersen
IPC分类号： H03M7/00
CPC分类号： H03H17/0621 , H03H2218/06
摘要： Systems and methods for converting a digital input data stream from a first sample rate to a second, fixed sample rate using a combination of hardware and software components. In one embodiment, a system includes a rate estimator configured to estimate the sample rate of an input data stream, a phase selection unit configured to select a phase for interpolation of a set of polyphase filter coefficients based on the estimated sample rate, a coefficient interpolator configured to interpolate the filter coefficients based on the selected phase, and a convolution unit configured to convolve the interpolated filter coefficients with samples of the input data stream to produce samples of a re-sampled output data stream. One or more hardware or software components are shared between multiple channels that can process data streams having independently variable sample rates.
摘要翻译： 用于使用硬件和软件组件的组合将数字输入数据流从第一采样率转换为第二固定采样率的系统和方法。 在一个实施例中，系统包括：速率估计器，被配置为估计输入数据流的采样率;相位选择单元，被配置为基于所估计的采样率来选择用于内插多相滤波器系数的相位;系数内插器 被配置为基于所选择的相位内插所述滤波器系数;以及卷积单元，其被配置为将所述内插滤波器系数与所述输入数据流的采样进行卷积，以产生重新采样的输出数据流的采样。 一个或多个硬件或软件组件在可以处理具有独立可变采样率的数据流的多个通道之间共享。
-
2.发明授权Systems and methods for implementing a sample rate converter using hardware and software to maximize speed and flexibility 有权使用硬件和软件实现采样率转换器的系统和方法，以最大限度地提高速度和灵活性公开(公告)号：US07167112B2
公开(公告)日：2007-01-23
申请号：US10805569
申请日：2004-03-20
IPC分类号： H03M7/00
CPC分类号： H03H17/0621 , H03H2218/06
摘要： Systems and methods for converting a digital input data stream from a first sample rate to a second, fixed sample rate using a combination of hardware and software components. In one embodiment, a system includes a rate estimator configured to estimate the sample rate of an input data stream, a phase selection unit configured to select a phase for interpolation of a set of polyphase filter coefficients based on the estimated sample rate, a coefficient interpolator configured to interpolate the filter coefficients based on the selected phase, and a convolution unit configured to convolve the interpolated filter coefficients with samples of the input data stream to produce samples of a re-sampled output data stream. One or more hardware or software components are shared between multiple channels that can process data streams having independently variable sample rates.
摘要翻译： 用于使用硬件和软件组件的组合将数字输入数据流从第一采样率转换为第二固定采样率的系统和方法。 在一个实施例中，系统包括：速率估计器，被配置为估计输入数据流的采样率;相位选择单元，被配置为基于所估计的采样率来选择用于内插多相滤波器系数的相位;系数内插器 被配置为基于所选择的相位内插所述滤波器系数;以及卷积单元，其被配置为将所述内插滤波器系数与所述输入数据流的采样进行卷积，以产生重新采样的输出数据流的采样。 一个或多个硬件或软件组件在可以处理具有独立可变采样率的数据流的多个通道之间共享。
-
公开(公告)号：US07729790B1
公开(公告)日：2010-06-01
申请号：US10805590
申请日：2004-03-19
摘要： Systems and methods for ensuring proper phase alignment of audio signals which are processed by separate hardware channels in an audio amplification system. In one embodiment, the phase alignment is controlled by determining the number of audio data samples which are stored in the input buffers of multiple audio amplification units and controlling reads from the input buffers to minimize the difference between an actual read-write pointer differential and a target differential. In a master unit, the target differential is a predetermined target value corresponding to a desired delay in the buffer. The actual pointer differential of the master unit is passed to one or more slave units. The actual pointer differential of the master unit is used as the target differential of the slave units. The pointer differentials of the slave units are thereby driven to track the pointer differential of the master unit, keeping the units synchronized.
摘要翻译： 用于确保音频信号的适当相位对准的系统和方法，其由音频放大系统中的分开的硬件通道处理。 在一个实施例中，通过确定存储在多个音频放大单元的输入缓冲器中的音频数据样本的数量来控制相位对准，并且控制来自输入缓冲器的读取以最小化实际读写指针差和 目标差异。 在主单元中，目标差分是与缓冲器中期望的延迟对应的预定目标值。 主单元的实际指针差分传递给一个或多个从单元。 主单元的实际指针差异用作从单元的目标差。 因此，从属单元的指针差异被驱动以跟踪主单元的指针差，保持单元同步。
-
公开(公告)号：US07286009B2
公开(公告)日：2007-10-23
申请号：US11324132
申请日：2005-12-30
申请人： Jack B. Andersen , Peter Craven , Michael A. Kost , Daniel L. W. Chieng , Larry E. Hand , Wilson E. Taylor
发明人： Jack B. Andersen , Peter Craven , Michael A. Kost , Daniel L. W. Chieng , Larry E. Hand , Wilson E. Taylor
IPC分类号： H03F3/68
CPC分类号： H03F3/217 , H03F1/32 , H03F2200/331
摘要： Systems and methods for performance improvements in digital switching amplifiers using simulation-based feedback. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a simulator configured to model processing of audio signals by the plant. The outputs of the plant and the simulator are provided to a subtractor, the output of which is then added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal for input to the subtractor. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.
-
公开(公告)号：US07576606B2
公开(公告)日：2009-08-18
申请号：US11782708
申请日：2007-07-25
申请人： Jack B. Andersen , Peter Craven , Michael A. Kost , Daniel L. W. Chieng , Larry E. Hand , Wilson E. Taylor
发明人： Jack B. Andersen , Peter Craven , Michael A. Kost , Daniel L. W. Chieng , Larry E. Hand , Wilson E. Taylor
IPC分类号： H03F3/38
CPC分类号： H03F3/217
摘要： Systems and methods for performance improvements in digital switching amplifiers using a low delay corrector. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low delay corrector configured to receive signals output by the plant. The output of the low delay corrector is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.
摘要翻译： 使用低延迟校正器的数字开关放大器性能改进的系统和方法。 在一个实施例中，数字脉宽调制（PWM）放大器包括被配置为接收和处理输入音频信号的信号处理设备。 放大器还包括低延迟校正器，其被配置为接收由工厂输出的信号。 低延迟校正器的输出作为反馈被添加到输入音频信号。 该设备可以由调制器和电源开关，噪声整形器或任何其它类型的设备组成。 可以提供模数转换器（ADC）以将输出音频信号转换为数字信号。 可以在ADC之前或之后实现滤波，如果ADC是过采样ADC，则可以在ADC之后放置抽取器。
-
公开(公告)号：USRE44525E1
公开(公告)日：2013-10-08
申请号：US13207232
申请日：2011-08-10
IPC分类号： H03F3/38
CPC分类号： H03F1/52 , H03F3/2173
摘要： Systems and methods for over-current protection in all-digital amplifiers using low-cost current sensing mechanisms. An over-current hard clipping unit receives a digital audio signal, clips the signal according to a clip level, and provides the signal to a modulator. The modulator modulates the signal to produce, e.g., a PWM signal and provides the modulated signal to an output stage which generates an output current to drive a speaker. An over-current sensing unit is compares the output current to a threshold value and generates a binary signal indicating whether the output current exceeds the threshold value. The hard clipping unit receives the binary signal and ramps down the clip level during time periods in which the binary signal indicates that the output current exceeds the threshold. When the binary signal indicates that the output current does not exceed the threshold value, the hard clipping unit ramps up the clip level.
摘要翻译： 使用低成本电流检测机制的全数字放大器中的过电流保护系统和方法。 过流硬切割单元接收数字音频信号，根据剪辑电平剪辑信号，并将信号提供给调制器。 调制器调制信号以产生例如PWM信号，并将调制信号提供给产生输出电流以驱动扬声器的输出级。 过流感测单元将输出电流与阈值进行比较，并产生指示输出电流是否超过阈值的二进制信号。 在二进制信号指示输出电流超过阈值的时间段期间，硬削波单元接收二进制信号并向下斜降电平。 当二进制信号指示输出电流不超过阈值时，硬限幅单元上升剪辑电平。
-
公开(公告)号：US07812666B2
公开(公告)日：2010-10-12
申请号：US12542634
申请日：2009-08-17
申请人： Daniel L. W. Chieng , Peter G. Craven , Michael A. Kost , Jack B. Andersen , Larry E. Hand , Wilson E. Taylor
发明人： Daniel L. W. Chieng , Peter G. Craven , Michael A. Kost , Jack B. Andersen , Larry E. Hand , Wilson E. Taylor
IPC分类号： H03F3/68
CPC分类号： H03F3/217
摘要： A low delay corrector (LDC) unit includes a non-linear function generator and a filter. The nonlinear function generator receives a first signal and outputs a second signal in dependence on the first signal and a transfer function of the nonlinear function generator. The filter is fed in dependence on the second signal output by the nonlinear function generator. The first signal received by the nonlinear function generator is derived in dependence on an input signal provided to an input of the LDC unit and an output of the filter. An output of the LDC unit is derived in dependence on the first signal received by the nonlinear function generator and the second signal output by the nonlinear function generator.
摘要翻译： 低延迟校正器（LDC）单元包括非线性函数发生器和滤波器。 非线性函数发生器接收第一信号并根据第一信号和非线性函数发生器的传递函数输出第二信号。 滤波器根据由非线性函数发生器输出的第二信号进给。 根据提供给LDC单元的输入的输入信号和滤波器的输出，导出由非线性函数发生器接收到的第一信号。 根据由非线性函数发生器接收到的第一信号和由非线性函数发生器输出的第二信号，导出LDC单元的输出。
-
公开(公告)号：US07728658B2
公开(公告)日：2010-06-01
申请号：US11782702
申请日：2007-07-25
申请人： Jack B. Andersen , Peter G. Craven , Michael A. Kost , Daniel L. W. Chieng , Larry E. Hand , Wilson E. Taylor
发明人： Jack B. Andersen , Peter G. Craven , Michael A. Kost , Daniel L. W. Chieng , Larry E. Hand , Wilson E. Taylor
CPC分类号： H03F1/3258 , H03F1/26 , H03F1/3241 , H03F3/217
摘要： Systems and methods for performance improvements in digital switching amplifiers using low-pass filtering to reduce noise and distortion. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low-pass filter configured to filter audio signals output by the plant. The filtered output of the plant is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.
摘要翻译： 使用低通滤波技术降低噪声和失真的数字开关放大器性能改进的系统和方法。 在一个实施例中，数字脉宽调制（PWM）放大器包括被配置为接收和处理输入音频信号的信号处理设备。 放大器还包括一个低通滤波器，用于滤除工厂输出的音频信号。 工厂的滤波输出作为反馈被添加到输入音频信号。 该设备可以由调制器和电源开关，噪声整形器或任何其它类型的设备组成。 可以提供模数转换器（ADC）以将输出音频信号转换为数字信号。 可以在ADC之前或之后实现滤波，如果ADC是过采样ADC，则可以在ADC之后放置抽取器。
-
公开(公告)号：US07286010B2
公开(公告)日：2007-10-23
申请号：US11340139
申请日：2006-01-26
IPC分类号： H03F3/38
CPC分类号： H03F1/52 , H03F3/2173
摘要： Systems and methods for over-current protection in all-digital amplifiers using low-cost current sensing mechanisms. An over-current hard clipping unit receives a digital audio signal, clips the signal according to a clip level, and provides the signal to a modulator. The modulator modulates the signal to produce, e.g., a PWM signal and provides the modulated signal to an output stage which generates an output current to drive a speaker. An over-current sensing unit is compares the output current to a threshold value and generates a binary signal indicating whether the output current exceeds the threshold value. The hard clipping unit receives the binary signal and ramps down the clip level during time periods in which the binary signal indicates that the output current exceeds the threshold. When the binary signal indicates that the output current does not exceed the threshold value, the hard clipping unit ramps up the clip level.
摘要翻译： 使用低成本电流检测机制的全数字放大器中的过电流保护系统和方法。 过流硬切割单元接收数字音频信号，根据剪辑电平剪辑信号，并将信号提供给调制器。 调制器调制信号以产生例如PWM信号，并将调制信号提供给产生输出电流以驱动扬声器的输出级。 过流感测单元将输出电流与阈值进行比较，并产生指示输出电流是否超过阈值的二进制信号。 在二进制信号指示输出电流超过阈值的时间段期间，硬削波单元接收二进制信号并向下斜降电平。 当二进制信号指示输出电流不超过阈值时，硬限幅单元上升剪辑电平。
-
10.发明授权Systems and methods for sample rate conversion using multiple rate estimate counters 失效使用多个速率估计计数器进行采样率转换的系统和方法公开(公告)号：US07474722B1
公开(公告)日：2009-01-06
申请号：US10805591
申请日：2004-03-19
IPC分类号： H04L7/00
CPC分类号： H03F3/217 , H03F2200/03 , H03H17/0275 , H03H17/0642 , H03H17/0685
摘要： Systems and methods for using multiple rate estimate counters in converting input data streams having variable sample rates to an output sample rate that are used in processing the data streams. In one embodiment, a system includes a clock source, first and second counters coupled to the clock source and configured to count cycles for corresponding data streams, and a data processor coupled to the first and second counters. The data processor is configured to read the number of cycles counted by each of the counters between received frame sync signals and to convert the first data stream to the predetermined output sample rate based on the corresponding number of cycles counted, and to convert the second data stream to the predetermined output sample rate based on the ratio of the numbers of cycles counted in the first and second counters.
摘要翻译： 用于将具有可变采样率的输入数据流转换为用于处理数据流的输出采样率的多个速率估计计数器的系统和方法。 在一个实施例中，系统包括时钟源，耦合到时钟源的第一和第二计数器，并且被配置为对相应数据流计数周期，以及耦合到第一和第二计数器的数据处理器。 数据处理器被配置为读取由接收到的帧同步信号之间的每个计数器计数的周期数，并且基于相应的计数周期将第一数据流转换成预定的输出采样率，并且将第二数据 基于在第一和第二计数器中计数的周期数的比率，将其流送到预定的输出采样率。
-
-
-
-
-
-
-
-
-
搜索结果
34 条记录 (耗时 0.032 秒)
