利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

16 条记录 (耗时 0.023 秒)

    Bi-directional display of circular arcs
    1.
    发明授权
    Bi-directional display of circular arcs 失效
    圆弧双向显示

    公开(公告)号：US4371933A

    公开(公告)日：1983-02-01

    申请号：US194522

    申请日：1980-10-06

    申请人： Jack E. Bresenham ,  Donald G. Grice ,  Shing-Chou Pi

    发明人： Jack E. Bresenham ,  Donald G. Grice ,  Shing-Chou Pi

    IPC分类号： G06F3/153 ,  G06K15/22 ,  G06T11/20 ,  G09G1/10 ,  G09G5/20 ,  G09G5/36 ,  G06F15/31

    CPC分类号： G06K15/22 ,  G09G1/10 ,  G09G5/20

    摘要： An improved method and apparatus are disclosed for generating circular arcs of any arc length greater than zero up to and including a full circle of 360 degrees. The method and apparatus can locate nonsymmetrical closest points for noninteger radius and arc center values. The method and apparatus is capable of generating the incremental move commands for drawing an arc either in the clockwise or counter clockwise direction which is a distinct advantage when used to drive a pen type electromechanical plotter. By dividing the generation of a 360 degree arc into eight octants, only two of the original eight directions need to be considered as candidate directions toward the next integer display matrix value to be displayed. The method and apparatus employ a novel initialization which provides a simple stopping test for any circular arc of arbitrary length and direction. Only simple addition and sign testing is used to display the circular arc.

    摘要翻译： 公开了一种改进的方法和装置，用于产生大于零直到并包括360度的整圆的任何弧长的圆弧。 该方法和装置可以定位非整数半径和圆弧中心值的非对称最近点。 该方法和装置能够产生用于沿顺时针或逆时针方向绘制弧的增量移动命令，这在用于驱动笔式机电绘图仪时是一个明显的优点。 通过将360度弧的生成除以八个八分圆，原始八个方向中只有两个需要被考虑作为要显示的下一个整数显示矩阵值的候选方向。 该方法和装置采用新颖的初始化，其为任意长度和方向的任何圆弧提供简单的停止测试。 仅使用简单的加法和符号测试来显示圆弧。

    Parallel computer network broadcasting and acknowledgement
    3.
    发明授权
    Parallel computer network broadcasting and acknowledgement 失效
    并行计算机网络广播和确认

    公开(公告)号：US6122277A

    公开(公告)日：2000-09-19

    申请号：US920348

    申请日：1997-08-19

    申请人： Derrick Garmire ,  Donald G. Grice ,  Tim Zhang

    发明人： Derrick Garmire ,  Donald G. Grice ,  Tim Zhang

    IPC分类号： H04L1/00 ,  H04L12/18 ,  H04L12/56 ,  H04L12/28

    CPC分类号： H04L47/10 ,  H04L12/1868 ,  H04L47/15 ,  H04L2001/0093

    摘要： Received portion of message is stored persistently and transmitted without awaiting receipt of another portion of the message and without generating a new message. The storing and transmitting can occur substantially simultaneously and be performed by one or more hardware elements. Originator of the message can choose whether to indicate indication of broadcasting of the message. First hardware element can determine local acknowledgement for message and second hardware element can determine determinative signal of the local acknowledgement and at least one of: one or more collected intended recipient acknowledgements for the message; and one or more collected determinative signals of intended recipient acknowledgements for the message.

    摘要翻译： 消息的接收部分被持久地存储并发送，而不等待接收消息的另一部分而不生成新消息。 存储和发送可以基本同时发生并且由一个或多个硬件元件执行。 消息的发起者可以选择是否指示消息的广播指示。 第一硬件元件可以确定消息的本地确认，并且第二硬件元件可以确定本地确认的确定性信号以及以下中的至少一个：消息的一个或多个收集的预期接收者确认; 以及针对消息的一个或多个收集确定信号的预期接收者确认。

    Method for interfacing components of a computing system with a pair of unidirectional, point-to-point buses
    5.
    发明授权
    Method for interfacing components of a computing system with a pair of unidirectional, point-to-point buses 失效
    用于将计算系统的组件与一对单向点对点总线接口的方法

    公开(公告)号：US07562171B2

    公开(公告)日：2009-07-14

    申请号：US11854004

    申请日：2007-09-12

    申请人： George W. Daly, Jr. ,  James S. Fields, Jr. ,  Donald G. Grice ,  Thomas K. Heller, Jr. ,  Appoloniel N. Tankeh

    发明人： George W. Daly, Jr. ,  James S. Fields, Jr. ,  Donald G. Grice ,  Thomas K. Heller, Jr. ,  Appoloniel N. Tankeh

    IPC分类号： G06F13/00 ,  G06F3/00 ,  H04L12/28

    CPC分类号： G06F13/4269

    摘要： A method of interfacing two components of a computing system is provided wherein the method includes providing a pair of unidirectional, point-to-point buses to transmit data between a master bus controller of the computing system and a slave bus controller of a processor unit of the computing system. The method also includes providing means for transmitting a command packet with an address associated with data pertaining to the command from the master bus controller to the slave bus controller. In addition, the method includes providing means for determining by the slave bus controller whether the slave bus controller can accept the command. The method further includes providing means for transmitting an acknowledgement from the slave bus controller to the master bus controller after the slave bus controller receives a first signaling interval for the command packet if the slave bus controller can accept the command packet.

    摘要翻译： 提供了一种接口计算系统的两个组件的方法，其中所述方法包括提供一对单向点对点总线以在所述计算系统的主总线控制器与所述计算系统的总线控制器之间传送数据， 计算系统。 该方法还包括提供用于发送具有与从主总线控制器到从总线控制器的命令有关的数据相关联的地址的命令分组的装置。 此外，该方法包括提供用于由从总线控制器确定从总线控制器是否可以接受命令的装置。 该方法还包括提供用于在从总线控制器接收到命令分组之后从属总线控制器接收到用于命令分组的第一信令间隔的从总线控制器向主总线控制器发送确认的装置。

    SYSTEM FOR FINE GRAINED FLOW-CONTROL CONCURRENCY TO PREVENT EXCESSIVE PACKET LOSS
    6.
    发明申请
    SYSTEM FOR FINE GRAINED FLOW-CONTROL CONCURRENCY TO PREVENT EXCESSIVE PACKET LOSS 审中-公开
    精细粒度流量控制系统，以防止过大的包装损失

    公开(公告)号：US20080049617A1

    公开(公告)日：2008-02-28

    申请号：US11466615

    申请日：2006-08-23

    申请人： Donald G. Grice ,  Kalyan C. Gunda ,  Brian D. Herr ,  Gautam H. Shah

    发明人： Donald G. Grice ,  Kalyan C. Gunda ,  Brian D. Herr ,  Gautam H. Shah

    IPC分类号： H04J1/16

    CPC分类号： H04L47/10 ,  H04L47/12 ,  H04L47/17 ,  H04L47/32

    摘要： A system for flow-control concurrency to prevent excessive packet loss, including at least one transmitter node. Each transmitter node is configured to transmit data. A first flow-control device is coupled to the at least one transmitter node. The first flow-control device is configured to limit the number of concurrent data replies sent by the at least one transmitter node such that the resources on the transmitter node side will not be overrun. At least one receive node is configured to receive data transmitted. The at least one receiver node is coupled to the at least one transmitter node via the communication network. A second flow-control device is coupled to the at least one receiver node. The second flow-control device is configured to limit the number of concurrent data requests received by the at least one receiver node such that the resources on the receiver node side will not be overrun.

    摘要翻译： 一种用于流控并发的系统，用于防止过多的分组丢失，包括至少一个发射机节点。 每个发射机节点被配置为发送数据。 第一流量控制装置耦合到所述至少一个发射器节点。 第一流量控制装置被配置为限制由至少一个发射机节点发送的并发数据回复的数量，使得发射机节点侧的资源不会超载。 至少一个接收节点被配置为接收发送的数据。 所述至少一个接收器节点经由所述通信网络耦合到所述至少一个发射机节点。 第二流量控制装置耦合到所述至少一个接收器节点。 第二流量控制装置被配置为限制由至少一个接收器节点接收的并发数据请求的数量，使得接收机节点侧的资源不会超载。

    Data processing system bus for multiple independent users
    7.
    发明授权
    Data processing system bus for multiple independent users 失效
    用于多个独立用户的数据处理系统总线

    公开(公告)号：US4451881A

    公开(公告)日：1984-05-29

    申请号：US317824

    申请日：1981-11-03

    申请人： Donald G. Grice ,  Frank E. Howley

    发明人： Donald G. Grice ,  Frank E. Howley

    IPC分类号： G06F13/374 ,  G06F3/04 ,  G06F9/46 ,  G06F15/16

    CPC分类号： G06F13/374

    摘要： A new bus permits processing elements (PE's) to communicate with other PE's entirely under the control of each PE without a separate bus controller. Each PE has means for broadcasting its priority code on a contention portion of the bus and for sampling the bus after a delay in which it has received the codes from other PE's. Each PE holds its priority code on the bus for a further delay during which other PE's can sample the priority code. The PE's resolve contention for access to the information portion of the bus in a multi stage contention sequence. System usage, made possible by peer-to-peer distribution of bus access control, includes dynamic driven priority schemes, a variety of operating modes and hence flexible multiplexing of message traffic.

    摘要翻译： 新的总线允许处理元件（PE）与其他PE完全在每个PE的控制下进行通信，而无需单独的总线控制器。 每个PE具有用于在总线的争用部分上广播其优先级代码并且在已经从其他PE接收到代码的延迟之后对总线进行采样的装置。 每个PE在总线上保持其优先级代码进一步延迟，其中PE可以对优先级代码进行采样。 PE在多阶段竞争序列中解决了访问总线信息部分的争用。 通过总线访问控制的点对点分发实现的系统使用包括动态驱动优先级方案，各种操作模式，从而可以灵活地复用消息业务。

    Method and system for interfacing components of a computing system with a pair of unidirectional, point-to-point buses
    8.
    发明授权
    Method and system for interfacing components of a computing system with a pair of unidirectional, point-to-point buses 失效
    用于将计算系统的组件与一对单向点对点总线接口的方法和系统

    公开(公告)号：US07568060B2

    公开(公告)日：2009-07-28

    申请号：US11304474

    申请日：2005-12-15

    申请人： George W. Daly, Jr. ,  James S. Fields, Jr. ,  Donald G. Grice ,  Thomas J. Heller ,  Appoloniel N. Tankeh

    发明人： George W. Daly, Jr. ,  James S. Fields, Jr. ,  Donald G. Grice ,  Thomas J. Heller ,  Appoloniel N. Tankeh

    IPC分类号： G06F13/00 ,  G06F13/42

    CPC分类号： G06F13/4269

    摘要： A method of interfacing two components of a computing system is provided wherein the method includes providing a pair of unidirectional, point-to-point buses to transmit data between a master bus controller of the computing system and a slave bus controller of a processor unit of the computing system. The method also includes providing means for transmitting a command packet with an address associated with data pertaining to the command from the master bus controller to the slave bus controller. In addition, the method includes providing means for determining by the slave bus controller whether the slave bus controller can accept the command. The method further includes providing means for transmitting an acknowledgement from the slave bus controller to the master bus controller after the slave bus controller receives a first signaling interval for the command packet if the slave bus controller can accept the command packet.

    摘要翻译： 提供了一种接口计算系统的两个组件的方法，其中所述方法包括提供一对单向点对点总线以在所述计算系统的主总线控制器与所述计算系统的总线控制器之间传送数据， 计算系统。 该方法还包括提供用于发送具有与从主总线控制器到从总线控制器的命令有关的数据相关联的地址的命令分组的装置。 此外，该方法包括提供用于由从总线控制器确定从总线控制器是否可以接受命令的装置。 该方法还包括：如果从总线控制器可以接收命令包，则在从总线控制器接收到命令分组的第一信令间隔之后，提供用于在从总线控制器向主总线控制器发送确认的装置。

    Scalable switch wiring technique for large arrays of processors
    9.
    发明授权
    Scalable switch wiring technique for large arrays of processors 失效
    用于大型处理器阵列的可扩展开关接线技术

    公开(公告)号：US5566342A

    公开(公告)日：1996-10-15

    申请号：US298828

    申请日：1994-08-31

    申请人： Monty M. Denneau ,  Donald G. Grice ,  Peter H. Hochschild ,  Craig B. Stunkel

    发明人： Monty M. Denneau ,  Donald G. Grice ,  Peter H. Hochschild ,  Craig B. Stunkel

    IPC分类号： G06F15/173 ,  G06F15/80 ,  G06F13/00

    CPC分类号： G06F15/17393

    摘要： Connections between the node switch sets associated with processors in large scalable processor arrays, such as those of the butterfly variety, are arranged, like the 2-D mesh array, in rows and columns between the node switch sets. Additional sets of switches called pivot switch sets are used to accomplish this. They are added to the processors and the processor switch sets to form processor clusters. The clusters are each assigned a logical row and column location in an array. Each pivot switch set is connected to all node switch sets in the same assigned column location and to all node switch sets in the same assigned row location as the pivot set. Consequently, any two node switch sets are connected by way of a pivot set located at either (a) the intersection row of the first node set and the column of the second node set or at (b) the intersection of the column of the first node set and the row of the second node set.

    摘要翻译： 在诸如蝴蝶品种的大型可扩展处理器阵列中的处理器相关联的节点开关组之间的连接在节点开关组之间的行和列中被布置成像2-D网格阵列。 称为枢转开关组的附加开关组用于实现这一点。 它们被添加到处理器和处理器交换机集合以形成处理器集群。 簇中的每一个都分配了数组中的逻辑行和列位置。 每个枢轴开关组连接到相同分配列位置中的所有节点开关组，并连接到与枢轴组相同的分配行位置中的所有节点开关组。 因此，任何两个节点交换机组通过位于（a）第一节点集合的交集行和第二节点集合的列的枢轴组连接，或者在（b）第一节点集合的列的交集处 节点集和第二个节点集的行。

    Advanced parallel array processor I/O connection
    10.
    发明授权
    Advanced parallel array processor I/O connection 失效
    高级并行阵列处理器I / O连接

    公开(公告)号：US5617577A

    公开(公告)日：1997-04-01

    申请号：US400687

    申请日：1995-03-08

    申请人： Thomas N. Barker ,  Clive A. Collins ,  Michael C. Dapp ,  James W. Dieffenderfer ,  Donald G. Grice ,  Billy J. Knowles ,  Donald M. Lesmeister ,  Richard E. Nier ,  Eric E. Retter ,  David B. Rolfe ,  Vincent J. Smoral

    发明人： Thomas N. Barker ,  Clive A. Collins ,  Michael C. Dapp ,  James W. Dieffenderfer ,  Donald G. Grice ,  Billy J. Knowles ,  Donald M. Lesmeister ,  Richard E. Nier ,  Eric E. Retter ,  David B. Rolfe ,  Vincent J. Smoral

    IPC分类号： G06F7/57 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00

    CPC分类号： G06F7/483 ,  G06F15/17337 ,  G06F15/17343 ,  G06F15/17381 ,  G06F15/8007

    摘要： A fast I/O for a multi-PME computer system provides a way to break into a network coupling to alternate network couplings. The system coupling is called a zipper.Our I/O zipper concept can be used to implement the concept that the port into a node could be driven by the port out of a node or by data coming from the system bus. Conversely, data being put out of a node would be available to both the input to another node and to the system bus. Outputting data to both the system bus and another node is not done simultaneously but in different cycles. The zipper passes data into and out of a network of interconnected nodes is used in a system of interconnecting nodes in a mesh, rings of wrapped tori. such that there is no edge to the network, the zipper mechanism logically breaks the the rings along a dimension orthogonal to the rings such that an edge to the network is established. The coupling dynamically toggles the network between a network without an edge and a network with an edge. Data passes into the network or out of the network through the edge when it is active, and the coupling permits dispersal of data entering the network or collection of data leaving the network such that the data rate through the edge matches both the sustained and peak data rates of the system external to the network.

    摘要翻译： 多PME计算机系统的快速I / O提供了一种方法，可以将网络耦合到备用网络耦合中。 系统耦合称为拉链。 我们的I / O拉链概念可用于实现端口到节点中的端口可以由节点驱动的端口或来自系统总线的数据的概念。 相反，放出节点的数据对于另一个节点和系统总线的输入将是可用的。 将数据输出到系统总线和另一个节点都不是同时进行，而是在不同的周期内完成。 拉链将数据传入和传出互连节点的网络用于网状互连节点的系统，包裹圆环的环。 使得网络没有边缘，拉链机构沿着与环正交的尺寸逻辑地断开环，使得建立到网络的边缘。 耦合动态地在无边缘的网络和具有边缘的网络之间切换网络。 当数据有效时，数据通过边缘进入网络或网络，并且耦合允许分散进入网络的数据或离开网络的数据收集，使得通过边缘的数据速率与持续和峰值数据匹配 网络外部系统的速率。