公开(公告)号：US07729195B2

公开(公告)日：2010-06-01

申请号：US11935887

申请日：2007-11-06

申请人： Jae-Youn Youn ,  Yoon-Hwan Yoon ,  Sang-Jae Rhee

发明人： Jae-Youn Youn ,  Yoon-Hwan Yoon ,  Sang-Jae Rhee

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C5/025 ,  G11C8/14

摘要： Semiconductor memory devices having hierarchical word line structures are provided. A block of sub-word line driver circuits (SWDB) are disposed between a first block of memory and a second block of memory. A SWDB includes a plurality of sub-wordline driver (SWD) circuits arranged in a plurality of SWD columns each having four SWD circuits extending in a first direction between the first and second blocks of memory. Two adjacent SWD columns include a SWD group for driving a plurality of sub-word lines extending from the SWD group along the first direction into the first and second blocks of memory.

摘要翻译： 提供具有分层字线结构的半导体存储器件。 一块子字线驱动电路（SWDB）设置在第一存储器块和第二存储器块之间。 SWDB包括布置在多个SWD列中的多个子字线驱动器（SWD）电路，每个SWD列具有在第一和第二存储器块之间沿第一方向延伸的四个SWD电路。 两个相邻的SWD列包括用于驱动从SWD组沿着第一方向延伸到第一和第二存储块的多个子字线的SWD组。

公开(公告)号：US20080112253A1

公开(公告)日：2008-05-15

申请号：US11935887

申请日：2007-11-06

申请人： Jae-Youn Youn ,  Yoon-Hwan Yoon ,  Sang-Jae Rhee

发明人： Jae-Youn Youn ,  Yoon-Hwan Yoon ,  Sang-Jae Rhee

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C5/025 ,  G11C8/14

摘要： Semiconductor memory devices having hierarchical word line structures are provided in which sub-word line driver circuitry is designed with layout patterns that enable increased integration density and high performance operation.

摘要翻译： 提供了具有分级字线结构的半导体存储器件，其中子字线驱动器电路被设计有能够提高集成密度和高性能操作的布局图案。

公开(公告)号：US20060179260A1

公开(公告)日：2006-08-10

申请号：US11348787

申请日：2006-02-07

申请人： Yoon-Hwan Yoon

发明人： Yoon-Hwan Yoon

IPC分类号： G06F13/00

CPC分类号： G11C11/4076 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1096 ,  G11C2207/2245

摘要： Provided are a semiconductor memory device and a data write and read method thereof. The semiconductor memory device includes a write data controller, an address controller, and a read data controller. The write data controller writes data received with an address to a first memory cell corresponding to the address and simultaneously stores the data in a data register. The address controller decodes and stores the address in an address register. The read data controller outputs data from a second memory cell corresponding to an address received with a data read command if the received address is different from the address stored in the address register, and outputs the data stored in the data register if the received address is equal to the address stored in the address register.

摘要翻译： 提供半导体存储器件及其数据写入和读取方法。 半导体存储器件包括写数据控制器，地址控制器和读数据控制器。 写数据控制器将与地址接收的数据写入与该地址对应的第一存储单元，同时将数据存储在数据寄存器中。 地址控制器将地址解码并存储在地址寄存器中。 如果接收到的地址与存储在地址寄存器中的地址不同，则读取数据控制器从与第二存储器单元相对应的地址输出数据，并且如果接收到的地址是 等于地址寄存器中存储的地址。

公开(公告)号：US07733738B2

公开(公告)日：2010-06-08

申请号：US11348787

申请日：2006-02-07

申请人： Yoon-Hwan Yoon

发明人： Yoon-Hwan Yoon

IPC分类号： G11C8/00

CPC分类号： G11C11/4076 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1096 ,  G11C2207/2245

摘要： Provided are a semiconductor memory device and a data write and read method thereof. The semiconductor memory device includes a write data controller, an address controller, and a read data controller. The write data controller writes data received with an address to a first memory cell corresponding to the address and simultaneously stores the data in a data register. The address controller decodes and stores the address in an address register. The read data controller outputs data from a second memory cell corresponding to an address received with a data read command if the received address is different from the address stored in the address register, and outputs the data stored in the data register if the received address is equal to the address stored in the address register.

摘要翻译： 提供半导体存储器件及其数据写入和读取方法。 半导体存储器件包括写数据控制器，地址控制器和读数据控制器。 写数据控制器将与地址接收的数据写入与该地址对应的第一存储单元，同时将数据存储在数据寄存器中。 地址控制器将地址解码并存储在地址寄存器中。 如果接收到的地址与存储在地址寄存器中的地址不同，则读取数据控制器从与第二存储器单元相对应的地址输出数据，并且如果接收到的地址是 等于地址寄存器中存储的地址。