公开(公告)号：US06969650B2

公开(公告)日：2005-11-29

申请号：US10629280

申请日：2003-07-29

申请人： Jae-sun Yun ,  Jin-hyun Shin

发明人： Jae-sun Yun ,  Jin-hyun Shin

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： Gate structures of a non-volatile integrated circuit memory device can include a thermal oxidation layer on a substrate beneath the gate structure that defines a side wall of the gate structure. An oxygen diffusion barrier layer is on the side wall of the gate structure and a floating gate is on the thermal oxidation layer and has a curved side wall portion. Related methods are also discussed.

摘要翻译： 非易失性集成电路存储器件的栅极结构可以包括限定栅极结构的侧壁的栅极结构下方的衬底上的热氧化层。 氧扩散阻挡层位于栅极结构的侧壁上，浮栅位于热氧化层上并具有弯曲的侧壁部分。 还讨论了相关方法。

公开(公告)号：US6153469A

公开(公告)日：2000-11-28

申请号：US352448

申请日：1999-07-13

申请人： Jae-sun Yun ,  Jeong-hyuk Choi ,  Chan-jo Lee

发明人： Jae-sun Yun ,  Jeong-hyuk Choi ,  Chan-jo Lee

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： An improved method of fabricating a flash memory cell is disclosed. A tunnel oxide film is formed on active regions. A first conductive film and a protective film are sequentially formed on the tunnel oxide film. The protective film on the isolation film is selectively etched, thus forming a protective film pattern on the tunnel oxide film. A sacrificial conductive film is formed on the resultant structure. The sacrificial conductive film and the first conductive film pattern are over-etched until the sidewalls and the upper surface of the protective film pattern are exposed, thereby exposing the center of the isolation film and simultaneously forming a first conductive film pattern having sloped sidewalls. With the present invention, an electrical field is prevented from being concentrated in an area between a control gate electrode and a floating gate because the floating gate have a sloped sidewall profile instead of sharp edges. Also, the recession of an isolation film between adjacent floating gates can be significantly avoided, consequently suppressing the deterioration of isolation between adjacent cells.

摘要翻译： 公开了一种制造闪存单元的改进方法。 隧道氧化膜形成在有源区上。 在隧道氧化膜上依次形成第一导电膜和保护膜。 选择性地蚀刻隔离膜上的保护膜，从而在隧道氧化膜上形成保护膜图案。 在所得结构上形成牺牲导电膜。 牺牲导电膜和第一导电膜图案被过度蚀刻直到保护膜图案的侧壁和上表面被暴露，从而暴露隔离膜的中心并同时形成具有倾斜侧壁的第一导电膜图案。 利用本发明，由于浮动栅极具有倾斜的侧壁轮廓而不是锋利的边缘，因此防止电场集中在控制栅极电极和浮动栅极之间的区域中。 此外，可以显着地避免相邻浮栅之间的隔离膜的衰退，从而抑制相邻单元之间的隔离的劣化。

公开(公告)号：US07920021B2

公开(公告)日：2011-04-05

申请号：US12580299

申请日：2009-10-16

申请人： Jin-Yong Oh ,  Sang-youn Jo ,  Joon-hee Lee ,  Jae-sun Yun ,  Seong-soo Kim

发明人： Jin-Yong Oh ,  Sang-youn Jo ,  Joon-hee Lee ,  Jae-sun Yun ,  Seong-soo Kim

IPC分类号： H01L25/00

CPC分类号： G11C16/10

摘要： A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented.

摘要翻译： 一种将线电压施加到包括多个有源区的半导体器件和使多个有源区绝缘的场区的方法，其中所述场区包括多根线。 该方法包括将半导体器件的操作所需的工作电压施加到多根导线中的至少一根，并将低于工作电压的电压施加到与多个有源区中的至少一个相邻的导线上， 多根电线。 因此，可以防止由于场区域的导线引起的由虚拟寄生晶体管引起的漏电流。

公开(公告)号：US20100207690A1

公开(公告)日：2010-08-19

申请号：US12580299

申请日：2009-10-16

申请人： Jin-Yong Oh ,  Sang-youn Jo ,  Joon-hee Lee ,  Jae-sun Yun ,  Seong-soo Kim

发明人： Jin-Yong Oh ,  Sang-youn Jo ,  Joon-hee Lee ,  Jae-sun Yun ,  Seong-soo Kim

IPC分类号： H03H11/24 ,  H03F3/14

CPC分类号： G11C16/10

摘要： A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented.

摘要翻译： 一种将线电压施加到包括多个有源区的半导体器件和使多个有源区绝缘的场区的方法，其中所述场区包括多根线。 该方法包括将半导体器件的操作所需的工作电压施加到多根导线中的至少一根，并将低于工作电压的电压施加到与多个有源区中的至少一个相邻的导线上， 多根电线。 因此，可以防止由于场区域的导线引起的由虚拟寄生晶体管引起的漏电流。

公开(公告)号：US20110249497A1

公开(公告)日：2011-10-13

申请号：US13070319

申请日：2011-03-23

申请人： Jae-sun Yun

发明人： Jae-sun Yun

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11573

摘要： Provided is a nonvolatile memory device. The nonvolatile memory device includes a substrate including a first region and a second region, which are spaced from each other. A string line group is disposed on the substrate in the first region, and a bias interconnection group is disposed above the substrate in the second region. The bias interconnection group includes a string select bias interconnection, cell bias interconnections, and a ground select bias interconnection, which are respectively electrically connected to a string select line, word lines, and a ground select line within the string line group. The string select bias interconnection is disposed between the ground select bias interconnection and the cell bias interconnections within the bias interconnection group.

摘要翻译： 提供了一种非易失性存储器件。 非易失性存储器件包括彼此间隔开的包括第一区域和第二区域的衬底。 在第一区域中的基板上设置串线组，在第二区域中的衬底上设置偏置互连组。 偏置互连组包括串选择偏置互连，单元偏置互连和接地选择偏置互连，其分别电连接到串线组内的串选择线，字线和接地选择线。 串选择偏置互连布置在偏置互连组内的接地选择偏置互连和单元偏置互连之间。