公开(公告)号：US4313173A

公开(公告)日：1982-01-26

申请号：US158246

申请日：1980-06-10

Applicant: James C. Candy ,  Bruce A. Wooley

Inventor： James C. Candy ,  Bruce A. Wooley

IPC: H03M1/66 ,  G06F17/17 ,  H04B14/04 ,  G06F15/34

CPC classification number: G06F17/17

Abstract: An interpolator is arranged to form an increment for each interpolation interval by dividing the difference between the interpolator input and output by a number N indicating the desired number of output samples in the interval. During each interval, the increment is repeatedly added to each output to form the next output.

Abstract translation: 内插器被布置为通过将内插器输入和输出之间的差除以指示在间隔中的期望输出样本数量的数字N来形成每个内插间隔的增量。 在每个间隔期间，增量重复添加到每个输出以形成下一个输出。

公开(公告)号：US4593271A

公开(公告)日：1986-06-03

申请号：US691947

申请日：1985-01-16

Applicant: James C. Candy

Inventor： James C. Candy

IPC: H03M1/68 ,  G06F3/05 ,  H03M1/00 ,  H03M1/08 ,  H03M1/66 ,  H03M3/04 ,  G06F7/38

CPC classification number: H03M1/661

Abstract: Digital signals are processed by a first accumulator to generate most significant bits which represent the signal to be converted but with truncation noise. The error signals from the first accumulator are processed by a second accumulator to generate a second set of most significant bits which are used to remove the truncation noise. The most significant bits from the second accumulator are converted to analog form, differentiated and then combined with the most significant bits from the first accumulator after being converted from digital to analog form. The combined signal is then amplified and filtered.

Abstract translation: 数字信号由第一累加器处理以产生表示要转换的信号但具有截断噪声的最高有效位。 来自第一累加器的误差信号由第二累加器处理以产生用于去除截断噪声的第二组最高有效位。 来自第二个累加器的最高有效位被转换成模拟形式，在从数字模式转换为模拟形式之后，将其与来自第一个累加器的最高有效位组合。 然后将组合的信号进行放大和滤波。

公开(公告)号：US4491982A

公开(公告)日：1985-01-01

申请号：US399140

申请日：1982-07-16

Applicant: James C. Candy ,  Bernard G. King

Inventor： James C. Candy ,  Bernard G. King

IPC: H04B10/10 ,  H04B9/00

CPC classification number: H04B10/1121

Abstract: A terrestrial light beam communication system is described for compatible utilization with existing radio transmission systems. The transmitter (FIG. 4) utilizes aiming means (41 and 42) to control the aim of the transmitted light beam. The receiver employs an array of detectors (FIG. 5) from which a circuit (FIG. 6) determines the position of the received light beam. The position of the received light beam is used to control the position of the transmitted light beam from which control signals are developed to maintain the aim of the transmitted light beam to combat the occurrence of ongoing fluctuations in the vertical deflection experienced by the transmitted light beam.

Abstract translation: 描述了与现有无线电传输系统兼容利用的陆地光束通信系统。 发射器（图4）利用瞄准装置（41和42）来控制透射光束的目的。 接收机采用一组检测器（图5），电路（图6）从该阵列确定接收的光束的位置。 接收光束的位置用于控制发射光束的位置，控制信号从该光束的显影位置保持透射光束的目的，以抵抗透射光束经历的垂直偏转中持续波动的发生 。

公开(公告)号：US4755794A

公开(公告)日：1988-07-05

申请号：US76649

申请日：1987-07-23

Applicant: James C. Candy

Inventor： James C. Candy

IPC: H04B14/04 ,  H03H17/06 ,  H03M7/38 ,  H03M7/00

CPC classification number: H03H17/0664

Abstract: The present invention relates to a digital-to-digital code converter, or decimator, which implements sinc.sup.3 processing. The input signal (X) to the code converter comprises a series of groups, each group including a series of N digital sample values occurring at high rate (1/.tau.) which are converted within the converter, using sinc.sup.3 processing, into a single digital value occurring at, for example, a (1/N).tau. rate for delivery to the converter output (Y). The code converter comprises three processing stages in cascade, where each stage includes separate accumulation means, each accumulation means arranged to add, during each series of N input sample values, the signal value received by that stage from the next preceding stage. Each of the three stages further includes a separate subprocessing means for processing the resultant accumulated digital value from the associated accumulation means at the end of each group period to produce a separated processed digital value which, when combined with the processed digital values from the other stages at the end of a group period, provides a single sinc.sup.3 processed digital value for the N input signal samples of each input group.

公开(公告)号：US4356559A

公开(公告)日：1982-10-26

申请号：US174516

申请日：1980-08-01

Applicant: James C. Candy ,  Bruce A. Wooley

Inventor： James C. Candy ,  Bruce A. Wooley

IPC: H03H17/04 ,  G06F15/34

CPC classification number: H03H17/04 ,  H03H17/0461

Abstract: A digital filter includes a pair of serially connected second order sections (200 and 260), each of which includes delay elements arranged to store the number of bits contained in two complete input words. Each filter section also includes simple logic (220, 230, 270 and 280) comprising adder circuits and inverters but no multipliers. The logic combines outputs from the delay element with the filter input to form an intermediate signal which is applied to the input of the delay element. The intermediate signal is also combined with yet other outputs from the delay element to form the filter output. To eliminate clocking complexity within the filter, the logic is not preset or cleared between each input word. Instead, the word length is intentionally increased, and the sign bit of each intermediate word is intentionally repeated as the word is processed in the filter, the extra bits acting as an inter-word buffer and serving to protect against spurious overflow and limit cycle oscillations.

Abstract translation: 数字滤波器包括一对串行连接的二阶部分（200和260），每一个部分包括被布置成存储包含在两个完整输入字中的位数的延迟元件。 每个滤波器部分还包括包括加法器电路和反相器但不包括乘法器的简单逻辑（220,230,270和280）。 该逻辑组合来自延迟元件的输出与滤波器输入，以形成施加到延迟元件的输入端的中间信号。 中间信号也与延迟元件的其它输出组合以形成滤波器输出。 为了消除滤波器内的时钟复杂度，逻辑不会在每个输入字之间预置或清零。 相反，字长被有意地增加，并且当该字在滤波器中被处理时，每个中间字的符号位被有意地重复，额外的位用作字间缓冲器，并用于防止虚假溢出和极限循环振荡 。

公开(公告)号：US4281318A

公开(公告)日：1981-07-28

申请号：US154843

申请日：1980-05-30

Applicant: James C. Candy ,  Bruce A. Wooley

Inventor： James C. Candy ,  Bruce A. Wooley

IPC: H03M7/02 ,  G06F7/544 ,  H03H17/06 ,  H04B14/04 ,  G06F5/06

CPC classification number: H03H17/0664 ,  G06F7/5443 ,  H03H17/0621

Abstract: A digital-to-digital converter is arranged to provide "decimated" output samples at rate f.sub.0, each of which represent a group of input samples received at a rate m times greater. Each output is generated using overlapped triangularly weighted accumulation on an interval including 2m preceding input samples. The samples near the beginning and end of each accumulation interval receive the smallest weight, and the samples at the middle of the interval receive the greatest weight. The converter is achievable in integrated circuit form using first and second serially connected accumulators, the first accumulating m input samples without weighting and the second being used to weight the samples so that the first receives m times the weight of the last sample. The output of the first accumulator is increased in scale by the factor "m" and the output of the second accumulator subtracted therefrom. The difference is delayed so that the next m samples may be accumulated. The output of the second accumulator is then combined with the delayed subtractor output to yield the desired overlapped, triangularly weighted accumulation.

Abstract translation: 数字 - 数字转换器被设置为以速率f0提供“抽取的”输出采样，每个输出样本表示以大于m倍的速率接收的一组输入样本。 每个输出都是使用重叠的三角加权积累产生的，包括前面输入样本2米的间隔。 每个累积间隔的开始和结束附近的样本接收到最小的权重，并且间隔中间的样本获得最大的权重。 该转换器可以使用第一和第二串联连接的累加器，第一次累加的m个输入样本而不加权，而第二个用于加权样本，使得第一个接收到最后一个样本的权重的m倍，以集成电路形式实现。 第一个累加器的输出按比例增加因子“m”，并从其中减去第二个累加器的输出。 差异被延迟，使得可以累积下一个m个样本。 然后将第二累加器的输出与延迟的减法器输出组合以产生期望的重叠的三角加权积累。