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公开(公告)号：US4359773A
公开(公告)日：1982-11-16
申请号：US166045
申请日：1980-07-07
申请人： Robert G. Swartz , Ping K. Tien , Bruce A. Wooley
发明人： Robert G. Swartz , Ping K. Tien , Bruce A. Wooley
CPC分类号： H01S5/0683 , H01S5/4031 , H04B10/032 , H01S5/02252 , H01S5/02284 , H01S5/0427 , H01S5/06213 , H01S5/06832
摘要： A plurality of semiconductor lasers (431-434) and a photodetector (120) are mounted on a silicon substrate (100) having an integrated circuit (101) fabricated therein. The integrated circuit includes a biasing circuit (405) for establishing a threshold current level that is dependent on the output of the photodetector and a modulator circuit (404) for providing a modulation current that is dependent on the digital values in an input signal. A semiconductor switch (406) selects only one of the plurality of semiconductor lasers for activation by the biasing and modulator circuits. The integrated circuit also includes a circuit (408) that operates the semiconductor switch so as to selectively activate a different one of the plurality of semiconductor lasers in response to either a predetermined output from said photodetector or in response to an external supervisory signal.
摘要翻译： 多个半导体激光器（431-434）和光电检测器（120）安装在其上制造有集成电路（101）的硅衬底（100）上。 集成电路包括用于建立取决于光电检测器的输出的阈值电流电平的偏置电路（405）和用于提供取决于输入信号中的数字值的调制电流的调制器电路（404）。 半导体开关（406）仅选择多个半导体激光器中的一个来激活偏置和调制电路。 集成电路还包括操作半导体开关的电路（408），以响应于来自所述光电检测器的预定输出或响应于外部监控信号来选择性地激活多个半导体激光器中的不同的半导体激光器。
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2.发明授权Radio frequency signal reception using frequency shifting by discrete-time sub-sampling down-conversion 失效射频信号接收使用频移采用离散时间子采样下变频
公开(公告)号：US5640698A
公开(公告)日：1997-06-17
申请号：US468280
申请日：1995-06-06
CPC分类号： H04B1/0025 , H03D7/00 , H04B1/0003 , H04B1/26
摘要： An RF communications receiver permits greater integration on standard silicon chips and consumes less power than previous receivers. Sub-sampling and discrete-time signal processing techniques are used to frequency down-convert, filter, amplify, and select a desired analog RF channel. A sample-and-hold circuit sub-samples the desired analog RF channel of carrier frequency f.sub.c, thereby down-converting it to a discrete-time image signal of frequency f.sub.i. Successive down-sampling, anti-alias filtering, and amplification of the discrete-time image signal yield a low-frequency discrete-time signal containing a down-converted channel of frequency f.sub.k. The low-frequency discrete-time signal is then digitized, filtered, and demodulated to reveal its baseband information content.
摘要翻译： RF通信接收器允许在标准硅芯片上实现更大的集成，并且比以前的接收机消耗更少的功率。 子采样和离散时间信号处理技术用于降频，滤波，放大和选择所需的模拟RF信道。 采样和保持电路对载波频率fc的所需模拟RF信道进行子采样，从而将其下变频到频率fi的离散时间图像信号。 离散时间图像信号的连续下采样，抗混叠滤波和放大产生包含频率为fk的下变频信道的低频离散时间信号。 然后对低频离散时间信号进行数字化，滤波和解调，以显示其基带信息内容。
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公开(公告)号：US4539554A
公开(公告)日：1985-09-03
申请号：US434876
申请日：1982-10-18
CPC分类号： H03K17/9643
摘要： An integrated array of pressure transducers capable of producing an analog output voltage representative of the applied pressure is proposed. The individual transducing elements (16) are defined by a three-layer structure including a thin layer of piezoelectric material (10) disposed between a reference potential plate (12) and a plurality of electrodes (15) contained in a silicon substrate (14). A force applied to a localized portion of the reference plate will cause a deflection of the piezoelectric material towards the electrodes on the substrate, inducing a capacitive charge on the electrode in the localized area. This capacitance is stores at a node A associated with the transducing element, and may be interrogated by a sensing circuit (18) located in the silicon substrate. Since the induced charge is directly proportional to the applied force, a measurement of the output voltage from node A will yield a direct indication of the localized force applied to the sensor.
摘要翻译： 提出了能够产生代表所施加的压力的模拟输出电压的集成的压力传感器阵列。 单个换能元件（16）由三层结构限定，该三层结构包括设置在参考电位板（12）和包含在硅衬底（14）中的多个电极之间的压电材料薄层， 。 施加到参考板的局部部分的力将引起压电材料朝向衬底上的电极的偏转，从而在局部区域中的电极上引起电容性电荷。 该电容存储在与转换元件相关联的节点A处，并且可以由位于硅衬底中的感测电路（18）询问。 由于感应电荷与施加的力成正比，因此来自节点A的输出电压的测量将产生施加到传感器的局部力的直接指示。
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公开(公告)号：US4313173A
公开(公告)日：1982-01-26
申请号：US158246
申请日：1980-06-10
申请人： James C. Candy , Bruce A. Wooley
发明人： James C. Candy , Bruce A. Wooley
CPC分类号： G06F17/17
摘要： An interpolator is arranged to form an increment for each interpolation interval by dividing the difference between the interpolator input and output by a number N indicating the desired number of output samples in the interval. During each interval, the increment is repeatedly added to each output to form the next output.
摘要翻译： 内插器被布置为通过将内插器输入和输出之间的差除以指示在间隔中的期望输出样本数量的数字N来形成每个内插间隔的增量。 在每个间隔期间，增量重复添加到每个输出以形成下一个输出。
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公开(公告)号：US4356559A
公开(公告)日：1982-10-26
申请号：US174516
申请日：1980-08-01
申请人： James C. Candy , Bruce A. Wooley
发明人： James C. Candy , Bruce A. Wooley
CPC分类号： H03H17/04 , H03H17/0461
摘要： A digital filter includes a pair of serially connected second order sections (200 and 260), each of which includes delay elements arranged to store the number of bits contained in two complete input words. Each filter section also includes simple logic (220, 230, 270 and 280) comprising adder circuits and inverters but no multipliers. The logic combines outputs from the delay element with the filter input to form an intermediate signal which is applied to the input of the delay element. The intermediate signal is also combined with yet other outputs from the delay element to form the filter output. To eliminate clocking complexity within the filter, the logic is not preset or cleared between each input word. Instead, the word length is intentionally increased, and the sign bit of each intermediate word is intentionally repeated as the word is processed in the filter, the extra bits acting as an inter-word buffer and serving to protect against spurious overflow and limit cycle oscillations.
摘要翻译： 数字滤波器包括一对串行连接的二阶部分（200和260），每一个部分包括被布置成存储包含在两个完整输入字中的位数的延迟元件。 每个滤波器部分还包括包括加法器电路和反相器但不包括乘法器的简单逻辑（220,230,270和280）。 该逻辑组合来自延迟元件的输出与滤波器输入，以形成施加到延迟元件的输入端的中间信号。 中间信号也与延迟元件的其它输出组合以形成滤波器输出。 为了消除滤波器内的时钟复杂度，逻辑不会在每个输入字之间预置或清零。 相反，字长被有意地增加，并且当该字在滤波器中被处理时，每个中间字的符号位被有意地重复，额外的位用作字间缓冲器，并用于防止虚假溢出和极限循环振荡 。
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公开(公告)号：US4281318A
公开(公告)日：1981-07-28
申请号：US154843
申请日：1980-05-30
申请人： James C. Candy , Bruce A. Wooley
发明人： James C. Candy , Bruce A. Wooley
CPC分类号： H03H17/0664 , G06F7/5443 , H03H17/0621
摘要： A digital-to-digital converter is arranged to provide "decimated" output samples at rate f.sub.0, each of which represent a group of input samples received at a rate m times greater. Each output is generated using overlapped triangularly weighted accumulation on an interval including 2m preceding input samples. The samples near the beginning and end of each accumulation interval receive the smallest weight, and the samples at the middle of the interval receive the greatest weight. The converter is achievable in integrated circuit form using first and second serially connected accumulators, the first accumulating m input samples without weighting and the second being used to weight the samples so that the first receives m times the weight of the last sample. The output of the first accumulator is increased in scale by the factor "m" and the output of the second accumulator subtracted therefrom. The difference is delayed so that the next m samples may be accumulated. The output of the second accumulator is then combined with the delayed subtractor output to yield the desired overlapped, triangularly weighted accumulation.
摘要翻译： 数字 - 数字转换器被设置为以速率f0提供“抽取的”输出采样，每个输出样本表示以大于m倍的速率接收的一组输入样本。 每个输出都是使用重叠的三角加权积累产生的，包括前面输入样本2米的间隔。 每个累积间隔的开始和结束附近的样本接收到最小的权重，并且间隔中间的样本获得最大的权重。 该转换器可以使用第一和第二串联连接的累加器，第一次累加的m个输入样本而不加权，而第二个用于加权样本，使得第一个接收到最后一个样本的权重的m倍，以集成电路形式实现。 第一个累加器的输出按比例增加因子“m”，并从其中减去第二个累加器的输出。 差异被延迟，使得可以累积下一个m个样本。 然后将第二累加器的输出与延迟的减法器输出组合以产生期望的重叠的三角加权积累。
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