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公开(公告)号：US5201041A
公开(公告)日：1993-04-06
申请号：US662339
申请日：1991-02-25
CPC分类号： G11C29/70 , G06F12/0848 , G06F12/0859 , G06F12/0888
摘要： An inpage buffer is used between a cache and slower storage device. When a processor requests data, the cache is checked to see if the data is already in the cache. If not, a request for the data is sent to the slower storage device. The buffer receives the data from the slower storage device and provides the data to the processor that requested the data. The buffer then provides the data to the cache for storage provided that the cache is not working on a separate storage request from the processor. The data will be written into the cache from the buffer when the cache is free from such requests. The buffer is also able to provide data corresponding to subsequent requests provided it contains such data. This may happen if a request for the same data occurs, and the buffer has not yet written the data into the cache. It can also occur if the areas of the cache which can hold data from an area of the slower storage is inoperable for some reason. The buffer acts as a minicache when such a catastrophic error in the cache occurs.
摘要翻译： 高速缓存和较慢存储设备之间使用内部缓冲区。 当处理器请求数据时，检查缓存以查看数据是否已经在高速缓存中。 如果没有，则将数据请求发送到较慢的存储设备。 缓冲区从较慢的存储设备接收数据，并将数据提供给请求数据的处理器。 缓冲区然后将数据提供给高速缓存用于存储，只要高速缓存不在与处理器的单独的存储请求上工作。 当缓存没有这样的请求时，数据将从缓冲区写入高速缓存。 缓冲区还能够提供对应于后续请求的数据，只要它包含这样的数据。 如果发生对相同数据的请求，并且缓冲区尚未将数据写入缓存，则可能会发生这种情况。 如果缓存中存储较慢存储区域的数据的区域由于某些原因而无法操作，也可能发生。 当缓存发生灾难性的错误时，缓冲区作为一个小时隙。
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公开(公告)号：US5008885A
公开(公告)日：1991-04-16
申请号：US291544
申请日：1988-12-29
IPC分类号： G06F11/22 , G06F11/00 , G06F11/26 , G06F11/267
CPC分类号： G06F11/2215 , G06F11/076 , G06F11/261
摘要： Programmable masks at ascending levels of processing machine functionality support the programmed injection of errors in response to machine events and machine states and in synchronism with machine operation. Provision is made for varying characteristics of injected errors through a programmable error mask and through generation of an injected error wave form having variable temporal and duration characteristics.
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3.发明授权Central processing unit checkpoint retry for store-in and store-through cache systems 失效中央处理单元检查点重试用于存储和存储缓存系统
公开(公告)号：US5418916A
公开(公告)日：1995-05-23
申请号：US592624
申请日：1990-10-04
CPC分类号： G06F11/1407 , G06F12/0811
摘要： A checkpoint retry system for recovery from an error condition in a multiprocessor type central processing unit which may have a store-in or a store-through cache system. At detection of a checkpoint instruction, the system initiates action to save the content of the program status word, the floating point registers, the access registers and the general purpose registers until the store operations are completed for the checkpointed sequence. For processors which have a store-in cache, modified cache data is saved in a store buffer until the checkpointed instructions are completed and then written to a cache which is accessible to other processors in the system. For processors which utilize store-through cache, the modified data for the checkpointed instructions is also stored in the store buffer prior to storage in the system memory.
摘要翻译： 用于从多处理器类型中央处理单元中的错误状态恢复的检查点重试系统，其可以具有存储或存储缓存系统。 在检查点指令检测时，系统发起动作以保存程序状态字，浮点寄存器，访问寄存器和通用寄存器的内容，直到对检查点序列完成存储操作。 对于具有存储缓存的处理器，将修改的高速缓存数据保存在存储缓冲区中，直到检查点指令完成，然后写入系统中其他处理器可访问的缓存。 对于使用直通缓存的处理器，在存储在系统存储器中之前，检查点指令的修改数据也被存储在存储缓冲器中。
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4.发明授权Apparatus and method for simultaneously presenting error interrupt and error data to a support processor 失效同时向支持处理器提供错误中断和错误数据的装置和方法
公开(公告)号：US5267246A
公开(公告)日：1993-11-30
申请号：US213560
申请日：1988-06-30
CPC分类号： G06F11/0772 , G06F11/2736
摘要： Apparatus and method for collecting and analyzing machine check interrupts generated by a central processor complex. Each logic card is scanned to detect the presence of error data generated by logic circuits on the card. A primary maintenance interface card collects the interrupt information identifying the interrupt as to type of interrupt and location of the card generating the interrupt. A system support adapter reports the collected interrupt information over a LAN to a support processor which may thereafter initiate diagnostic operations with the central processor complex.
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公开(公告)号：US20100326608A1
公开(公告)日：2010-12-30
申请号：US12491333
申请日：2009-06-25
申请人： Yu-Che Wen , Ju-Sheng Cheng , Kevin C. Huang
发明人： Yu-Che Wen , Ju-Sheng Cheng , Kevin C. Huang
CPC分类号： E06B9/326 , E06B9/262 , E06B2009/2622 , E06B2009/3265
摘要： The invention relates to a secure lock for a lift cord of a window blind or shade, which includes a head rail, a bottom rail and a shading unit combined between the head rail and the bottom rail. The shading unit has plural connecting members respectively engaging with an annular secure lock, except the connecting member positioned closest to the bottom rail engaging with a cap-shaped secure lock instead. A lift cord is strung in the annular secure locks, with the end fastened with the cap-shaped secure lock. An opening is formed in a ring of the annular secure locks and a groove formed in a curved portion of the cap-shaped secure lock. Thus, the lift cord can be released if an object is accidentally trapped between the lift cord and the shading unit, achieving a secure effect.
摘要翻译： 本发明涉及一种用于窗帘或遮帘的提升绳的安全锁，其包括头轨，底轨和组合在头轨和底轨之间的遮光单元。 阴影单元具有多个连接构件，分别与环形固定锁相接合，除了最靠近底轨定位的连接构件与帽形安全锁相配合。 一个电梯绳被插在环形安全锁中，端部用帽形安全锁扣固定。 开口形成在环形固定锁的环中，以及形成在帽形安全锁的弯曲部分中的槽。 因此，如果物体被意外地夹在提升绳和遮阳单元之间，则电梯线可以被释放，达到安全的效果。
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公开(公告)号：US5398331A
公开(公告)日：1995-03-14
申请号：US910193
申请日：1992-07-08
申请人： Kevin C. Huang , David A. Wise
发明人： Kevin C. Huang , David A. Wise
CPC分类号： G06F11/1683 , G06F11/1633 , G06F11/2082 , G06F2201/835
摘要： A computing system constructed of multiple processing elements containing private storage, attached to a shared global storage, is called a closely-coupled system. Each processing element may be a single processing unit (PU) with private storage, or a tightly coupled multi-processor unit with private storage. Either type of processing element will be referred to as a Central Processor Complex (CPC), the computing system complex as a whole is referred to as a sysplex. IBM ESA/390 processors provide examples of both single and multi-processor CPC's. For a highly-available shared storage for data-sharing in a multi-processing element environment, highly-available shared storage is provided by a duplexed controllers with non-volatile storage, which is accessed by tightly connected Processing Elements as a single logical copy. Our duplexed controllers provide not only the shared data but also the control information necessary for multi-Processing Element data management with speed-matching processor. The duplexed controllers, including a primary and backup controller, are always synchronized to execute each message command to ensure that they do not diverge. Each controller of the duplexed controller receives its own command from a Processing Element and reaches consensus with other controller to synchronize command execution and return a response code to the Processing Element. To sequence and synchronize the command execution by each of the duplexed controller, a tightly-synchronized Sysplex timer is used to time-stamp each command and response so that the duplexed controllers will run in synchronism. When an "out of sync" condition is detected by a SSC, the monitoring information of SSC and integrated SP, and the result of diagnostics are used to determine the faulty SSC of a the duplexed SSC.
摘要翻译： 由包含附属于共享全局存储器的私有存储器的多个处理元件构成的计算系统被称为紧密耦合的系统。 每个处理元件可以是具有专用存储器的单个处理单元（PU）或具有私人存储器的紧密耦合的多处理器单元。 任何一种类型的处理元件将被称为中央处理器复合体（CPC），整个计算系统复杂度被称为系统复合体。 IBM ESA / 390处理器提供单处理器和多处理器CPC的示例。 对于高可用性共享存储器，用于在多处理元件环境中进行数据共享，高可用性共享存储由具有非易失性存储器的双工控制器提供，该存储器由紧密连接的处理元素作为单个逻辑副本访问。 我们的双工控制器不仅提供共享数据，还提供了具有速度匹配处理器的多处理元件数据管理所需的控制信息。 双工控制器（包括主控和备用控制器）总是同步执行每条消息命令，以确保它们不发散。 双工控制器的每个控制器从处理元件接收其自己的命令，并与其他控制器达成一致，以同步命令执行并将响应代码返回给处理元件。 为了对每个双工控制器的命令执行顺序和同步，使用紧密同步的Sysplex定时器来对每个命令和响应进行时间戳，以便双工控制器将同步运行。 当SSC检测到“不同步”条件时，SSC和集成SP的监控信息以及诊断结果用于确定双工SSC的故障SSC。
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