EXECUTING ROUTINES BETWEEN AN EMULATED OPERATING SYSTEM AND A HOST OPERATING SYSTEM
    1.
    发明申请
    EXECUTING ROUTINES BETWEEN AN EMULATED OPERATING SYSTEM AND A HOST OPERATING SYSTEM 审中-公开
    在仿真操作系统和主机操作系统之间执行程序

    公开(公告)号:US20100205400A1

    公开(公告)日:2010-08-12

    申请号:US12367858

    申请日:2009-02-09

    IPC分类号: G06F9/455 G06F9/30

    CPC分类号: G06F9/45554

    摘要: Approaches for emulating an operating system. A method includes executing a first operating system (OS) on an instruction processor. The first OS includes instructions of a first instruction set that are native to the instruction processor. A second OS is emulated on the first OS and includes instructions of a second instruction set that are not native to the instruction processor. An emulated transfer-of-control instruction is determined during emulation of the second OS to target either instructions of the first set or the second set. In response to determining that instructions of the first set are targeted, control is transferred to the targeted instructions of the first set on the instruction processor. In response to determining that instructions of the second set are targeted, the targeted instructions of the second set are retrieved and emulated.

    摘要翻译: 模拟操作系统的方法。 一种方法包括在指令处理器上执行第一操作系统(OS)。 第一OS包括指令处理器本地的第一指令集的指令。 在第一OS上仿真第二个OS,并且包括第二指令集的指令,该第二指令集不是指令处理器本地的。 在第二OS的仿真期间确定仿真的控制转移指令以对准第一组或第二组的指令。 响应于确定第一组的指令是目标,控制被转移到指令处理器上的第一组的目标指令。 响应于确定第二组的指令是目标,第二组的目标指令被检索和仿真。

    EVENT LOGGER FOR JUST-IN-TIME STATIC TRANSLATION SYSTEM
    3.
    发明申请
    EVENT LOGGER FOR JUST-IN-TIME STATIC TRANSLATION SYSTEM 审中-公开
    一次性静态转换系统的事件记录

    公开(公告)号:US20130262820A1

    公开(公告)日:2013-10-03

    申请号:US13432416

    申请日:2012-03-28

    IPC分类号: G06F9/30

    摘要: Systems and methods for event logging in a just-in-time static translation system are disclosed. One method includes executing a workload in a computing system having a native instruction set architecture, the workload stored in one or more banks of non-native instructions. At least a portion of the workload is further included in one or more banks of native instructions and executing the workload comprises executing at least part of the workload from the one or more banks of native instructions. The method also includes determining an amount of time during execution of the workload in which the execution of the workload occurs from the one or more banks of native instructions. The method includes generating a log including performance statistics generated during execution of the workload, the performance statistics including the amount of time.

    摘要翻译: 公开了在即时静态翻译系统中事件记录的系统和方法。 一种方法包括在具有本地指令集架构的计算系统中执行工作负载,所述工作负载存储在一个或多个非本地指令组中。 工作负载的至少一部分还包括在一个或多个本地指令组中,并且执行工作负载包括从一个或多个本机指令行执行至少一部分工作负载。 该方法还包括确定在执行工作负荷的执行期间的时间量,其中工作负荷的执行从一个或多个本机指令组发生。 该方法包括生成包括在执行工作负载期间生成的性能统计的日志,该性能统计包括时间量。

    SYSTEMS AND METHODS FOR DEBUGGING JUST-IN-TIME STATIC TRANSLATION IN AN EMULATED SYSTEM
    4.
    发明申请
    SYSTEMS AND METHODS FOR DEBUGGING JUST-IN-TIME STATIC TRANSLATION IN AN EMULATED SYSTEM 审中-公开
    系统和方法,用于调试模拟系统中的一次性静态转换

    公开(公告)号:US20130132063A1

    公开(公告)日:2013-05-23

    申请号:US13299452

    申请日:2011-11-18

    IPC分类号: G06F9/455 G06F9/45

    摘要: Systems and methods for testing and validation of translated memory banks used in an emulated system are disclosed. One method includes translating one or more banks of non-native instructions into one or more banks of native instructions executable in a computing system having a native instruction set architecture. The one or more banks of non-native instructions define one or more tests of execution of a non-native instruction set architecture. The method also includes loading a memory with instructions and data defined according to the non-native instruction set architecture and addressed by the one or more tests, and triggering, by an emulator, execution of the translated one or more banks of native instructions. The method further includes, upon detection of an error during execution of the translated one or more banks of native instructions, identifying an error in execution of the non-native instruction set architecture by the computing system.

    摘要翻译: 公开了一种用于仿真系统中使用的翻译存储体的测试和验证的系统和方法。 一种方法包括将一组或多组非本地指令转换成具有本机指令集架构的计算系统中可执行的一个或多个本地指令库。 一个或多个非本机指令组定义了非本地指令集架构的一个或多个执行测试。 该方法还包括加载具有根据非本机指令集架构定义并由一个或多个测试寻址的指令和数据的存储器,以及由仿真器触发翻译的一个或多个本地指令库的执行。 该方法还包括:在执行翻译的一个或多个本机指令段期间检测到错误时,识别由计算系统执行非本地指令集架构的错误。

    JUST-IN-TIME STATIC TRANSLATION SYSTEM FOR EMULATED COMPUTING ENVIRONMENTS
    5.
    发明申请
    JUST-IN-TIME STATIC TRANSLATION SYSTEM FOR EMULATED COMPUTING ENVIRONMENTS 审中-公开
    用于模拟计算环境的一次性静态翻译系统

    公开(公告)号:US20130132061A1

    公开(公告)日:2013-05-23

    申请号:US13299458

    申请日:2011-11-18

    IPC分类号: G06F9/455

    摘要: A computing system and method of executing a software program and translation of instructions for an emulated computing environment. The computing system includes a programmable circuit capable of executing native instructions of a first instruction set architecture and incapable of executing non-native instructions of a second instruction set architecture. The emulator operates within an interface layer and translates non-native applications hosted within an emulated operating system for execution. The computing system includes translated memory banks defined at least in part by the emulated operating system and capable of native execution on the programmable circuit, where the emulated operating system is incapable of execution on the programmable circuit. The computing system includes a linker configured to manage association of at least one of the one or more translated memory banks to the interface layer for native execution by the programmable circuit in place of a corresponding bank of non-native instructions.

    摘要翻译: 一种用于执行软件程序的计算系统和方法以及用于仿真计算环境的指令的翻译。 计算系统包括能够执行第一指令集架构的本机指令并且不能执行第二指令集架构的非本地指令的可编程电路。 仿真器在接口层内运行,并且转换托管在仿真操作系统中的非本机应用程序以供执行。 计算系统包括至少部分由仿真的操作系统定义的翻译的存储器组,并且能够在可编程电路上进行本地执行,其中仿真操作系统不能在可编程电路上执行。 计算系统包括链接器,其被配置为管理一个或多个翻译的存储器组中的至少一个与接口层的关联,用于由可编程电路代替相应的非本机指令组进行本地执行。

    Operating system scheduler/dispatcher with randomized resource allocation and user manipulable weightings
    6.
    发明授权
    Operating system scheduler/dispatcher with randomized resource allocation and user manipulable weightings 有权
    具有随机资源分配和用户可操纵权重的操作系统调度器/调度器

    公开(公告)号:US07058949B1

    公开(公告)日:2006-06-06

    申请号:US10038547

    申请日:2001-10-19

    IPC分类号: G06F9/46

    CPC分类号: G06F9/4881

    摘要: This invention provides to large-scale operating systems supporting multiple classes of tasks a method to allocate processor resources to the classes according to a probability model. It is useful in preventing a class from being denied resources by giving it positive measure in the model. A first stage probability algorithm assigns classes of tasks to an IP resource available to a given scheduler queue. Each class is allocated a probability level in a lottery-type draw in this first stage. In preferred embodiments, a second stage probability algorithm is used to assign tasks within a class to an available processor resource. This second stage algorithm is biased in a feedback manner by task resource usage history. Tasks of extreme high or low priority may avoid the probabilistic mechanisms in preferred embodiments.

    摘要翻译: 本发明提供了支持多类任务的大型操作系统,根据概率模型将处理器资源分配给类。 通过在模型中给予积极的措施来防止类被拒绝资源是有用的。 第一级概率算法将任务类分配给给定调度程序队列可用的IP资源。 在这个第一阶段,每个类都被分配了彩票抽奖的概率级别。 在优选实施例中,使用第二级概率算法将类中的任务分配给可用的处理器资源。 该第二阶段算法以任务资源使用历史的反馈方式偏置。 在优选实施例中,极高或低优先级的任务可以避免概率机制。

    Hierarchical affinity dispatcher for task management in a multiprocessor computer system
    7.
    发明授权
    Hierarchical affinity dispatcher for task management in a multiprocessor computer system 有权
    多处理器计算机系统中任务管理的分层关联调度器

    公开(公告)号:US06996822B1

    公开(公告)日:2006-02-07

    申请号:US09920023

    申请日:2001-08-01

    IPC分类号: G06F9/46

    CPC分类号: G06F9/5083 G06F9/5033

    摘要: An Operating System (OS) function maps affinity to processors for each new task and except for certain circumstances where other processors are permitted to steal tasks, this affinity remains unchanged. Hierarchical load balancing is mapped through an affinity matrix (that can be expressed as a table) which is accessed by executable code available through a dispatcher to the multiplicity of instruction processors (IPs) in a multiprocessor computer system. Since the computer system has multiple layers of cache memories, connected by busses, and crossbars to the main memory, the hierarchy mapping matches the cache memories to assign tasks first to IPs most likely to share the same cache memory residue from related tasks, or at least less likely to incur a large access time cost. Each IP has its own switching queue (SQ) for primary task assignments through which the OS makes the initial affinity assignment. When an IP's SQ becomes task free, the dispatcher code has the free IP look to the SQ of other IPs in accord with the mapped hierarchy, if a threshold of idleness is reached.

    摘要翻译: 操作系统(OS)功能将对每个新任务的处理器的亲和性映射到除了允许其他处理器窃取任务的某些情况之外,此关联性保持不变。 分层负载平衡通过亲和度矩阵(可以表示为表格)进行映射,该矩阵可以通过调度程序可用的可执行代码访问多处理器计算机系统中的多个指令处理器(IP)。 由于计算机系统具有通过总线连接的多层高速缓冲存储器和与主存储器交叉的多层缓存存储器,所以层次映射匹配高速缓存存储器以将任务首先分配给最有可能从相关任务共享相同高速缓存存储器残留的IP,或者在 最不容易产生大的访问时间成本。 每个IP都有自己的切换队列(SQ)用于主要任务分配,OS通过该交换队列进行初始的亲和性分配。 当IP的SQ无任务时,如果达到空闲阈值,则调度程序代码将具有符合映射层级的其他IP的SQ的空闲IP外观。