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    Multiple level built-in self-test controller and method therefor
    1.
    发明授权
    Multiple level built-in self-test controller and method therefor 失效
    多级内置自检控制器及其方法

    公开(公告)号：US06760865B2

    公开(公告)日：2004-07-06

    申请号：US09859324

    申请日：2001-05-16

    申请人： James S. Ledford ,  Alex S. Yap ,  Robert A. Jensen ,  Brian E. Cook ,  Mark S. Aurora

    发明人： James S. Ledford ,  Alex S. Yap ,  Robert A. Jensen ,  Brian E. Cook ,  Mark S. Aurora

    IPC分类号： G06F1100

    CPC分类号： G11C29/1201 ,  G06F13/1694 ,  G11C16/04 ,  G11C29/16 ,  G11C2029/0401

    摘要： An integrated circuit has a Built-In Self-Test (BIST) controller (10) that has a sequencer (16) that provides test algorithm information for multiple memories (44, 46, 48, 50). The sequencer identifies the test algorithm that is to be performed and multiple memory interfaces (32, 34, 36, 38) interpret the output of the sequencer and perform the algorithm on the multiple memories. The multiple memories may be different or the same regarding type, size, data widths, etc. Having multiple memory interfaces provides flexibility to tailor the test algorithm for each memory, but yet keeps the advantage of a single source of identifying the test algorithm. With the memories being non-volatile, timing information with regard to the test algorithm is stored in the memories. This timing information is read prior to performing the test algorithm and is used in performing the test algorithm.

    摘要翻译： 集成电路具有内置自检（BIST）控制器（10），其具有为多个存储器（44,46,48,50）提供测试算法信息的定序器（16）。 定序器识别要执行的测试算法，多个存储器接口（32,34,36,38）解释定序器的输出并在多个存储器上执行算法。 多个存储器可以在类型，大小，数据宽度等方面是不同的或相同的。具有多个存储器接口提供了灵活性来为每个存储器定制测试算法，但是仍保持识别测试算法的单一来源的优点。 由于存储器是非易失性的，关于测试算法的定时信息被存储在存储器中。 在执行测试算法之前读取该定时信息，并用于执行测试算法。

    Recording of result information in a built-in self-test circuit and method therefor
    2.
    发明授权
    Recording of result information in a built-in self-test circuit and method therefor 有权
    在内置的自检电路中记录结果信息及其方法

    公开(公告)号：US06347056B1

    公开(公告)日：2002-02-12

    申请号：US09859333

    申请日：2001-05-16

    申请人： James S. Ledford ,  Alex S. Yap ,  Brian E. Cook

    发明人： James S. Ledford ,  Alex S. Yap ,  Brian E. Cook

    IPC分类号： G11C700

    CPC分类号： G11C29/44

    摘要： An integrated circuit has a Built-In Self-Test (BIST) controller (10) that has a sequencer (16) that provides test algorithm information for multiple memories (44, 46, 48, 50). The sequencer identifies the test algorithm that is to be performed and multiple memory interfaces (32, 34, 36, 38) interpret the output of the sequencer and perform the algorithm on the multiple memories. The multiple memories may be different or the same regarding type, size, data widths, etc. Having multiple memory interfaces provides flexibility to tailor the test algorithm for each memory, but yet keeps the advantage of a single source of identifying the test algorithm. With the memories being non-volatile, timing information with regard to the test algorithm is stored in the memories. When test algorithms fail or complete execution, pertinent BIST information is stored in non-user addressable space of the multiple memories.

    摘要翻译： 集成电路具有内置自检（BIST）控制器（10），其具有为多个存储器（44,46,48,50）提供测试算法信息的定序器（16）。 定序器识别要执行的测试算法，多个存储器接口（32,34,36,38）解释定序器的输出并在多个存储器上执行算法。 多个存储器可以在类型，大小，数据宽度等方面是不同的或相同的。具有多个存储器接口提供了灵活性来为每个存储器定制测试算法，但是仍保持识别测试算法的单一来源的优点。 由于存储器是非易失性的，关于测试算法的定时信息被存储在存储器中。 当测试算法失败或完成执行时，相关BIST信息存储在多个存储器的非用户可寻址空间中。