公开(公告)号：US20090055563A1

公开(公告)日：2009-02-26

申请号：US12259942

申请日：2008-10-28

申请人： James Stephen Fields, JR. ,  Paul Frank Lecocq ,  Brian Chan Monwai ,  Thomas Pflueger ,  Kevin Franklin Reick ,  Timothy M. Skergan ,  Scott Barnett Swaney

发明人： James Stephen Fields, JR. ,  Paul Frank Lecocq ,  Brian Chan Monwai ,  Thomas Pflueger ,  Kevin Franklin Reick ,  Timothy M. Skergan ,  Scott Barnett Swaney

IPC分类号： G06F13/42

CPC分类号： G06F15/161

摘要： In-band firmware executes instructions which cause commands to be sent on a coherency fabric. Fabric snoop logic monitors the coherency fabric for command packets that target a resource in one of the support chips attached via an FSI link. Conversion logic converts the information from the fabric packet into an FSI protocol. An FSI command is transmitted via the FSI transmit link to an FSI slave of the intended support chip. An FSI receive link receives response data from the FSI slave of the intended support chip. Conversion logic converts the information from the support chip received via the FSI receive link into the fabric protocol. Response packet generation logic generates the fabric response packet and returns it on the coherency fabric. An identical FSI link between a support processor and support chips allows direct access to the same resources on the support chips by out-of-band firmware.

摘要翻译： 带内固件执行指令，使指令在一致性结构上发送。 Fabric Snoop逻辑监视针对通过FSI链接附加的支持芯片之一的资源的命令包的一致性结构。 转换逻辑将信息从Fabric数据包转换为FSI协议。 FSI命令通过FSI传输链路发送到预期支持芯片的FSI从站。 FSI接收链路从预期的支持芯片的FSI从站接收响应数据。 转换逻辑将从通过FSI接收链路接收的支持芯片的信息转换为结构协议。 响应分组生成逻辑生成结构响应分组并将其返回到一致性结构上。 支持处理器和支持芯片之间的相同FSI链路允许通过带外固件直接访问支持芯片上的相同资源。

公开(公告)号：US20090083489A1

公开(公告)日：2009-03-26

申请号：US12325266

申请日：2008-12-01

申请人： Leo James Clark ,  James Stephen Fields, JR. ,  Guy Lynn Guthrie ,  William John Starke

发明人： Leo James Clark ,  James Stephen Fields, JR. ,  Guy Lynn Guthrie ,  William John Starke

IPC分类号： G06F12/08

CPC分类号： G06F12/0851 ,  G06F12/0811

摘要： A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first directory to access the first array slice while using a second directory to access the second array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In one embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. The cache array is arranged with rows and columns of cache sectors wherein a cache line is spread across sectors in different rows and columns, with a portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency.

摘要翻译： 缓存存储器将具有单个访问/命令端口的高速缓存阵列逻辑地分区成至少两个切片，并且使用第一目录来访问第一阵列片，同时使用第二目录来访问第二阵列片，但是从高速缓存目录 使用控制单个访问/命令端口的单个缓存仲裁器进行管理。 在一个实施例中，每个高速缓存目录具有其自己的目录仲裁器来处理冲突的内部请求，并且目录仲裁器与高速缓存仲裁器通信。 高速缓存阵列布置有高速缓存扇区的行和列，其中高速缓存行分布在不同行和列中的扇区之间，其中一部分给定高速缓存行位于具有第一延迟的第一列中，并且给定的另一部分 高速缓存线位于具有大于第一等待时间的第二等待时间的第二列中。

公开(公告)号：US20090049248A1

公开(公告)日：2009-02-19

申请号：US11839663

申请日：2007-08-16

申请人： Leo James Clark ,  James Stephen Fields, JR. ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Phillip G. Williams

发明人： Leo James Clark ,  James Stephen Fields, JR. ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Phillip G. Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0851 ,  G06F12/0864

摘要： A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.

摘要翻译： 一种方法和计算机系统，用于通过重新配置扇区到片分配和较低的高速缓存寻址方案来减少具有扇区和分片的低级高速缓存的高速缓存子系统中的布线拥塞，所需的房地产和访问延迟。 通过这种分配，具有不连续地址的扇区被放置在相同的片内，并且基于对高速缓存片内的可寻址扇区的这种重新分配，可以在两级低级高速缓存之间进行简化布线方案。 此外，低速缓存有效地址标签被重新配置，使得先前分配用于识别扇区和片的地址字段相对于地址标签内的彼此的位置被切换。 地址位的这种重新分配使得能够基于指示的扇区进行直接片寻址。