公开(公告)号：US07698478B2

公开(公告)日：2010-04-13

申请号：US11523330

申请日：2006-09-19

Applicant: James Wang ,  Choon Ping Chng ,  Mark D. Hayter ,  Ruchi Wadhawan

Inventor： James Wang ,  Choon Ping Chng ,  Mark D. Hayter ,  Ruchi Wadhawan

IPC: G06F3/00

CPC classification number: H04L47/10 ,  G06F13/28 ,  G06F13/385 ,  H04L47/39

Abstract: In one embodiment, a system comprises at least one processor and a peripheral interface controller coupled to the processor. Further coupled to receive transactions from a peripheral interface, the peripheral interface controller is configured to accumulate freed credits for a given transaction type of a plurality of transaction types that are not yet returned to a transmitter on the peripheral interface. The peripheral interface controller is also configured to cause transmission of a flow control update transaction on the peripheral interface responsive to a number of the freed credits exceeding a threshold amount that is less than a total number of credits allocated to the given transaction type.

Abstract translation: 在一个实施例中，系统包括耦合到处理器的至少一个处理器和外围接口控制器。 进一步耦合以从外围接口接收事务，外围接口控制器被配置为为尚未返回到外围接口上的发射机的多个事务类型的给定事务类型累积释放的信用。 外围接口控制器还被配置为响应于多个释放的信用超过超过分配给给定交易类型的信用总数的阈值量而在外围接口上传输流量控制更新交易。

公开(公告)号：US07930462B2

公开(公告)日：2011-04-19

申请号：US11756931

申请日：2007-06-01

Applicant: James Wang ,  Choon Ping Chng

Inventor： James Wang ,  Choon Ping Chng

IPC: G06F3/00 ,  G06F13/12 ,  G06F13/40 ,  G06F13/00 ,  H04L12/28

CPC classification number: G06F13/385 ,  G06Q20/20

Abstract: In one embodiment, an apparatus comprises serializer/deserializer (SERDES) circuits. Each SERDES circuit provides data received from a respective lane to which the SERDES circuit is coupled. A receive pipe is coupled to the SERDES circuits and comprises accumulate buffers, multiplexing levels, accumulate buffer counters, control registers, and control logic. Each accumulate buffer corresponds to a respective port configurable over the plurality of lanes. A first level of the multiplexing levels is coupled to receive data from neighboring lanes on one input and the data from the neighboring lanes connected in reverse order on the other input. Each multiplexor at each other level is coupled to receive outputs of neighboring multiplexors from a next lower level on one input and the outputs connected in reverse order on the other input. Each configuration register corresponds to a respective port, indicating an initial lane assigned to the respective port and a size of the port. The control logic is configured to generate select signals responsive to respective bits of the buffer counters and respective bits of initial lane numbers.

Abstract translation: 在一个实施例中，一种装置包括串行器/解串器（SERDES）电路。 每个SERDES电路提供从SERDES电路耦合到的相应通道接收的数据。 接收管耦合到SERDES电路，包括累加缓冲器，复用电平，累加缓冲器计数器，控制寄存器和控制逻辑。 每个累积缓冲器对应于可在多个通道上配置的相应端口。 多路复用电平的第一级被耦合以从一个输入上的相邻通道接收数据，并且在另一个输入上从相邻通道反向连接的数据。 每个其他级别的每个多路复用器被耦合以从一个输入端的下一个较低电平接收相邻多路复用器的输出，而另一个输入端以相反的顺序连接。 每个配置寄存器对应于相应的端口，指示分配给相应端口的初始通道和端口的大小。 控制逻辑被配置为响应于缓冲器计数器的各个位和初始通道号的相应位产生选择信号。

公开(公告)号：US20080126606A1

公开(公告)日：2008-05-29

申请号：US11523330

申请日：2006-09-19

Applicant: James Wang ,  Choon Ping Chng ,  Mark D. Hayter ,  Ruchi Wadhawan

Inventor： James Wang ,  Choon Ping Chng ,  Mark D. Hayter ,  Ruchi Wadhawan

IPC: G06F3/00

CPC classification number: H04L47/10 ,  G06F13/28 ,  G06F13/385 ,  H04L47/39

Abstract: In one embodiment, a system comprises at least one processor and a peripheral interface controller coupled to the processor. Further coupled to receive transactions from a peripheral interface, the peripheral interface controller is configured to accumulate freed credits for a given transaction type of a plurality of transaction types that are not yet returned to a transmitter on the peripheral interface. The peripheral interface controller is also configured to cause transmission of a flow control update transaction on the peripheral interface responsive to a number of the freed credits exceeding a threshold amount that is less than a total number of credits allocated to the given transaction type.

Abstract translation: 在一个实施例中，系统包括耦合到处理器的至少一个处理器和外围接口控制器。 进一步耦合以从外围接口接收事务，外围接口控制器被配置为为尚未返回到外围接口上的发射机的多个事务类型的给定事务类型累积释放的信用。 外围接口控制器还被配置为响应于多个释放的信用超过超过分配给给定交易类型的信用总数的阈值量而在外围接口上传输流量控制更新交易。

公开(公告)号：US20080300992A1

公开(公告)日：2008-12-04

申请号：US11756931

申请日：2007-06-01

Applicant: James Wang ,  Choon Ping Chng

Inventor： James Wang ,  Choon Ping Chng

IPC: G06Q20/00 ,  G07G1/12

CPC classification number: G06F13/385 ,  G06Q20/20

Abstract: In one embodiment, an apparatus comprises serializer/deserializer (SERDES) circuits. Each SERDES circuit provides data received from a respective lane to which the SERDES circuit is coupled. A receive pipe is coupled to the SERDES circuits and comprises accumulate buffers, multiplexing levels, accumulate buffer counters, control registers, and control logic. Each accumulate buffer corresponds to a respective port configurable over the plurality of lanes. A first level of the multiplexing levels is coupled to receive data from neighboring lanes on one input and the data from the neighboring lanes connected in reverse order on the other input. Each multiplexor at each other level is coupled to receive outputs of neighboring multiplexors from a next lower level on one input and the outputs connected in reverse order on the other input. Each configuration register corresponds to a respective port, indicating an initial lane assigned to the respective port and a size of the port. The control logic is configured to generate select signals responsive to respective bits of the buffer counters and respective bits of initial lane numbers.

Abstract translation: 在一个实施例中，一种装置包括串行器/解串器（SERDES）电路。 每个SERDES电路提供从SERDES电路耦合到的相应通道接收的数据。 接收管耦合到SERDES电路，包括累加缓冲器，复用电平，累加缓冲器计数器，控制寄存器和控制逻辑。 每个累积缓冲器对应于可在多个通道上配置的相应端口。 多路复用电平的第一级被耦合以从一个输入上的相邻通道接收数据，并且在另一个输入上从相邻通道反向连接的数据。 每个其他级别的每个多路复用器被耦合以从一个输入端的下一个较低电平接收相邻多路复用器的输出，而另一个输入端以相反的顺序连接。 每个配置寄存器对应于相应的端口，指示分配给相应端口的初始通道和端口的大小。 控制逻辑被配置为响应于缓冲器计数器的各个位和初始通道号的相应位产生选择信号。

公开(公告)号：US07054898B1

公开(公告)日：2006-05-30

申请号：US09632235

申请日：2000-08-04

Applicant: Allan Tzungren Tzeng ,  Choon Ping Chng

Inventor： Allan Tzungren Tzeng ,  Choon Ping Chng

IPC: G06F7/38

CPC classification number: G06F7/485 ,  G06F7/49915 ,  G06F7/49947 ,  G06F7/49952 ,  G06F7/49957

Abstract: A processor having a floating point execution unit with improved parallelism in the adder (add/subtract) unit is disclosed. A preferred aspect of the invention is a new use of the compare logic in the floating point execution unit, coupled with an end-around-carry bit value calculator, to allow the correct rounding choice of the operands to be made before the mantissa portions of the operands are subtracted (added) rather than after.

Abstract translation: 公开了一种具有在加法器（加/减）单元中具有改进的并行性的浮点执行单元的处理器。 本发明的优选方面是浮点执行单元中的比较逻辑与结尾进位位值计算器的新用途，以允许在操作数的尾数部分之前进行操作数的正确舍入选择 减去（添加）操作数，而不是之后。

公开(公告)号：US06772187B1

公开(公告)日：2004-08-03

申请号：US09586657

申请日：2000-06-01

Applicant: Michael L. Ott ,  Choon Ping Chng ,  Tzungren Allen Tzeng

Inventor： Michael L. Ott ,  Choon Ping Chng ,  Tzungren Allen Tzeng

IPC: G06F750

CPC classification number: G06F7/026 ,  G06F7/508

Abstract: Disclosed herein is an apparatus and method for determining if a first number is greater than or equal to a second number. By analyzing nibbles of a multi-bit number in parallel to determine for each nibble if the nibbles are unequal and if a first nibble is greater than a second nibble and thereafter logically determining which of the highest order nibbles, if any, are unequal to discover whether the first number is greater than the second number, or determining that all nibble pairs are equal and thus concluding that both numbers are equal. A digital logic circuit is preferably employed for such analysis.

Abstract translation: 本文公开了一种用于确定第一数量是否大于或等于第二数量的装置和方法。 通过并行分析多位数的半字节来确定每个半字节是否不平等，如果第一个半字节大于第二个半字节，然后逻辑上确定哪个最高阶的半字节（如果有的话）不等于发现 第一个数字是否大于第二个数字，或者确定所有半字节对是相等的，从而得出两个数字相等的结论。 数字逻辑电路优选用于这种分析。

公开(公告)号：US06760891B2

公开(公告)日：2004-07-06

申请号：US10113423

申请日：2002-04-01

Applicant: Choon Ping Chng

Inventor： Choon Ping Chng

IPC: G06F1750

CPC classification number: G01R31/318357 ,  G01R31/2891 ,  G01R31/31705 ,  G06F17/5022

Abstract: An abstract register transfer level (RTL) model that simulates behavior of a dynamic circuit is created. The model is built upon an existing RTL with another level of abstraction capturing input transitions.

Abstract translation: 创建模拟动态电路行为的抽象寄存器传输级（RTL）模型。 该模型建立在具有另一个抽象级别的现有RTL捕获输入转换的基础之上。

公开(公告)号：US06647404B2

公开(公告)日：2003-11-11

申请号：US10217740

申请日：2002-08-12

Applicant: Tzungren Allan Tzeng ,  Choon Ping Chng

Inventor： Tzungren Allan Tzeng ,  Choon Ping Chng

IPC: G06F752

CPC classification number: G06F7/5324 ,  G06F7/4876 ,  G06F7/49994 ,  G06F7/5338

Abstract: A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double precision multiplication is accomplished by generating a plurality of partial products and summing these in the carry-save partial-product accumulator. The partial-product accumulator has a carry-save adder, a sum register, a carry-out counter and an extender. The carry-out counter receives a carry outputs of the carry-save adder and array multiplier, and the extender is coupled to extend the sum register dependent upon the contents of the carry-out counter. The extension occurs during addition of the most significant partial product to the sum of less significant partial products.

公开(公告)号：US06446104B1

公开(公告)日：2002-09-03

申请号：US09396236

申请日：1999-09-15

Applicant: Tzungren Allan Tzeng ,  Choon Ping Chng

Inventor： Tzungren Allan Tzeng ,  Choon Ping Chng

IPC: G06F744

CPC classification number: G06F7/5324 ,  G06F7/4876 ,  G06F7/49994 ,  G06F7/5338

Abstract: A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double precision multiplication is accomplished by generating a plurality of partial products and summing these in the carry-save partial-product accumulator. The partial-product accumulator has a carry-save adder, a sum register, a carry-out counter and an extender. The carry-out counter receives a carry outputs of the carry-save adder and array multiplier, and the extender is coupled to extend the sum register dependent upon the contents of the carry-out counter. The extension occurs during addition of the most significant partial product to the sum of less significant partial products.

Abstract translation: 用于处理器的浮点流水线的双精度乘法器具有阵列乘法器和进位保存部分乘积累加器。 通过生成多个部分乘积并在进位保存部分乘积累加器中求和这些来实现双精度乘法。 部分积累器具有进位保存加法器，和寄存器，进位计数器和扩展器。 进位计数器接收进位存储加法器和阵列乘法器的进位输出，并且扩展器被耦合以根据执行计数器的内容来扩展和寄存器。 在将最重要的部分产品添加到不太重要的部分产品的总和中时，延伸发生。