公开(公告)号：US07698478B2

公开(公告)日：2010-04-13

申请号：US11523330

申请日：2006-09-19

申请人： James Wang ,  Choon Ping Chng ,  Mark D. Hayter ,  Ruchi Wadhawan

发明人： James Wang ,  Choon Ping Chng ,  Mark D. Hayter ,  Ruchi Wadhawan

IPC分类号： G06F3/00

CPC分类号： H04L47/10 ,  G06F13/28 ,  G06F13/385 ,  H04L47/39

摘要： In one embodiment, a system comprises at least one processor and a peripheral interface controller coupled to the processor. Further coupled to receive transactions from a peripheral interface, the peripheral interface controller is configured to accumulate freed credits for a given transaction type of a plurality of transaction types that are not yet returned to a transmitter on the peripheral interface. The peripheral interface controller is also configured to cause transmission of a flow control update transaction on the peripheral interface responsive to a number of the freed credits exceeding a threshold amount that is less than a total number of credits allocated to the given transaction type.

摘要翻译： 在一个实施例中，系统包括耦合到处理器的至少一个处理器和外围接口控制器。 进一步耦合以从外围接口接收事务，外围接口控制器被配置为为尚未返回到外围接口上的发射机的多个事务类型的给定事务类型累积释放的信用。 外围接口控制器还被配置为响应于多个释放的信用超过超过分配给给定交易类型的信用总数的阈值量而在外围接口上传输流量控制更新交易。

公开(公告)号：US20080126606A1

公开(公告)日：2008-05-29

申请号：US11523330

申请日：2006-09-19

申请人： James Wang ,  Choon Ping Chng ,  Mark D. Hayter ,  Ruchi Wadhawan

发明人： James Wang ,  Choon Ping Chng ,  Mark D. Hayter ,  Ruchi Wadhawan

IPC分类号： G06F3/00

CPC分类号： H04L47/10 ,  G06F13/28 ,  G06F13/385 ,  H04L47/39

摘要： In one embodiment, a system comprises at least one processor and a peripheral interface controller coupled to the processor. Further coupled to receive transactions from a peripheral interface, the peripheral interface controller is configured to accumulate freed credits for a given transaction type of a plurality of transaction types that are not yet returned to a transmitter on the peripheral interface. The peripheral interface controller is also configured to cause transmission of a flow control update transaction on the peripheral interface responsive to a number of the freed credits exceeding a threshold amount that is less than a total number of credits allocated to the given transaction type.

摘要翻译： 在一个实施例中，系统包括耦合到处理器的至少一个处理器和外围接口控制器。 进一步耦合以从外围接口接收事务，外围接口控制器被配置为为尚未返回到外围接口上的发射机的多个事务类型的给定事务类型累积释放的信用。 外围接口控制器还被配置为响应于多个释放的信用超过超过分配给给定交易类型的信用总数的阈值量而在外围接口上传输流量控制更新交易。

公开(公告)号：US07930462B2

公开(公告)日：2011-04-19

申请号：US11756931

申请日：2007-06-01

申请人： James Wang ,  Choon Ping Chng

发明人： James Wang ,  Choon Ping Chng

IPC分类号： G06F3/00 ,  G06F13/12 ,  G06F13/40 ,  G06F13/00 ,  H04L12/28

CPC分类号： G06F13/385 ,  G06Q20/20

摘要： In one embodiment, an apparatus comprises serializer/deserializer (SERDES) circuits. Each SERDES circuit provides data received from a respective lane to which the SERDES circuit is coupled. A receive pipe is coupled to the SERDES circuits and comprises accumulate buffers, multiplexing levels, accumulate buffer counters, control registers, and control logic. Each accumulate buffer corresponds to a respective port configurable over the plurality of lanes. A first level of the multiplexing levels is coupled to receive data from neighboring lanes on one input and the data from the neighboring lanes connected in reverse order on the other input. Each multiplexor at each other level is coupled to receive outputs of neighboring multiplexors from a next lower level on one input and the outputs connected in reverse order on the other input. Each configuration register corresponds to a respective port, indicating an initial lane assigned to the respective port and a size of the port. The control logic is configured to generate select signals responsive to respective bits of the buffer counters and respective bits of initial lane numbers.

摘要翻译： 在一个实施例中，一种装置包括串行器/解串器（SERDES）电路。 每个SERDES电路提供从SERDES电路耦合到的相应通道接收的数据。 接收管耦合到SERDES电路，包括累加缓冲器，复用电平，累加缓冲器计数器，控制寄存器和控制逻辑。 每个累积缓冲器对应于可在多个通道上配置的相应端口。 多路复用电平的第一级被耦合以从一个输入上的相邻通道接收数据，并且在另一个输入上从相邻通道反向连接的数据。 每个其他级别的每个多路复用器被耦合以从一个输入端的下一个较低电平接收相邻多路复用器的输出，而另一个输入端以相反的顺序连接。 每个配置寄存器对应于相应的端口，指示分配给相应端口的初始通道和端口的大小。 控制逻辑被配置为响应于缓冲器计数器的各个位和初始通道号的相应位产生选择信号。

公开(公告)号：US20080300992A1

公开(公告)日：2008-12-04

申请号：US11756931

申请日：2007-06-01

申请人： James Wang ,  Choon Ping Chng

发明人： James Wang ,  Choon Ping Chng

IPC分类号： G06Q20/00 ,  G07G1/12

CPC分类号： G06F13/385 ,  G06Q20/20

摘要： In one embodiment, an apparatus comprises serializer/deserializer (SERDES) circuits. Each SERDES circuit provides data received from a respective lane to which the SERDES circuit is coupled. A receive pipe is coupled to the SERDES circuits and comprises accumulate buffers, multiplexing levels, accumulate buffer counters, control registers, and control logic. Each accumulate buffer corresponds to a respective port configurable over the plurality of lanes. A first level of the multiplexing levels is coupled to receive data from neighboring lanes on one input and the data from the neighboring lanes connected in reverse order on the other input. Each multiplexor at each other level is coupled to receive outputs of neighboring multiplexors from a next lower level on one input and the outputs connected in reverse order on the other input. Each configuration register corresponds to a respective port, indicating an initial lane assigned to the respective port and a size of the port. The control logic is configured to generate select signals responsive to respective bits of the buffer counters and respective bits of initial lane numbers.

摘要翻译： 在一个实施例中，一种装置包括串行器/解串器（SERDES）电路。 每个SERDES电路提供从SERDES电路耦合到的相应通道接收的数据。 接收管耦合到SERDES电路，包括累加缓冲器，复用电平，累加缓冲器计数器，控制寄存器和控制逻辑。 每个累积缓冲器对应于可在多个通道上配置的相应端口。 多路复用电平的第一级被耦合以从一个输入上的相邻通道接收数据，并且在另一个输入上从相邻通道反向连接的数据。 每个其他级别的每个多路复用器被耦合以从一个输入端的下一个较低电平接收相邻多路复用器的输出，而另一个输入端以相反的顺序连接。 每个配置寄存器对应于相应的端口，指示分配给相应端口的初始通道和端口的大小。 控制逻辑被配置为响应于缓冲器计数器的各个位和初始通道号的相应位产生选择信号。

公开(公告)号：US11093992B2

公开(公告)日：2021-08-17

申请号：US15970188

申请日：2018-05-03

申请人： James Wang ,  Siddharth Biswal

发明人： James Wang ,  Siddharth Biswal

IPC分类号： G06Q30/00 ,  G06Q30/06 ,  G06Q50/16 ,  H04L12/58 ,  H04L29/08 ,  G06Q50/00

摘要： Systems and methods are described for efficiently meeting the needs of property buyers, sellers, and agents. Attributes of the user and of each property are combined and processed by a machine learning model. The output represents a prediction that a user will choose to view the property. Each property is ranked and displayed to the user. When the user selects a property, the interaction is used to update the machine learning model. In some cases, a natural language processing system identifies property and user attributes based on a natural language query. In some cases, a chatbot may respond to a natural language query in real time. The system may also be utilized to provide matching services for buyers or sellers to agents, or third party service providers, as well as matching buyers and sellers directly to each other, or user to other users for transaction, interaction and other needs.

公开(公告)号：US20180278215A1

公开(公告)日：2018-09-27

申请号：US15983678

申请日：2018-05-22

申请人： James Wang ,  Yuh-Min Lin ,  Kun-You Lin

发明人： James Wang ,  Yuh-Min Lin ,  Kun-You Lin

IPC分类号： H03F1/30 ,  H03F1/56 ,  H03F3/16 ,  H01L27/02

CPC分类号： H03F1/301 ,  H01L27/0255 ,  H01L27/0292 ,  H03F1/523 ,  H03F1/56 ,  H03F3/16 ,  H03F3/193 ,  H03F3/72 ,  H03F2200/18 ,  H03F2200/222 ,  H03F2200/294 ,  H03F2200/387 ,  H03F2200/426 ,  H03F2200/444 ,  H03F2200/447 ,  H03F2200/451 ,  H03F2203/7231 ,  H03F2203/7236

摘要： A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

公开(公告)号：US20180269575A1

公开(公告)日：2018-09-20

申请号：US15984912

申请日：2018-05-21

申请人： James Wang

发明人： James Wang

IPC分类号： H01Q3/26 ,  G01S3/14

CPC分类号： H01Q3/2605 ,  G01S3/14

摘要： An array antenna system consists of layered construct of subarrays. Each beam pointing angle requires an antenna weight vector (AWV). A circuit tracks the changing orientation of a beam within a much larger virtual array of antenna weights. A row or column of a local RAM may be determined to be least likely to be read next and is overwritten with antenna weights more likely to be read next. An address translation circuit represents the RAM as a barrel. An adaptively adjusted antenna weight method optimizes received signal power. A beam splitting method provides a mirror beam pointing direction by wrapping around a look ahead table of antenna weight vectors when an antenna is itself gyrating or when a remote transceiver is anticipated to transit the horizon.

公开(公告)号：US20180253780A1

公开(公告)日：2018-09-06

申请号：US15970188

申请日：2018-05-03

申请人： James Wang ,  Siddharth Biswal

发明人： James Wang ,  Siddharth Biswal

IPC分类号： G06Q30/06 ,  G06Q50/16 ,  H04L12/58 ,  H04L29/08

CPC分类号： G06Q30/0631 ,  G06Q30/0627 ,  G06Q30/0641 ,  G06Q50/01 ,  G06Q50/16 ,  H04L51/02 ,  H04L51/32 ,  H04L67/22 ,  H04L67/306

摘要： Systems and methods are described for efficiently meeting the needs of property buyers, sellers, and agents. Attributes of the user and of each property are combined and processed by a machine learning model. The output represents a prediction that a user will choose to view the property. Each property is ranked and displayed to the user. When the user selects a property, the interaction is used to update the machine learning model. in some cases, a natural language processing system identifies property and user attributes based on a natural language query. In some cases, a chatbot may respond to a natural language query in real time. The system may also be utilized to provide matching services for buyers or sellers to agents, or third party service providers, as well as matching buyers and sellers directly to each other, or user to other users for transaction, interaction and other needs.

公开(公告)号：US10027028B2

公开(公告)日：2018-07-17

申请号：US15162405

申请日：2016-05-23

申请人： James Wang ,  Chak Chie

发明人： James Wang ,  Chak Chie

IPC分类号： H01Q3/00 ,  H01Q3/30 ,  H01Q1/22 ,  H01Q21/00 ,  H01Q21/06 ,  H01Q3/26 ,  H01Q3/34

摘要： A method of operation for a hierarchically elaborated phased-array antenna. Within a plurality of front end modules a phased-array processing die individually transforms phase and gain according to a register array. The register array in each RFIC is grouped into a local register group and a global register group, the local registers physically placed close in proximity to RF chains which each correspond to an element of array antenna, whereby each set of local registers control an individual antenna element and a global register controlling overall RFIC function. The method efficiently elaborates phase shift weights into a submodule of a phase array antenna system. Within each subarray phase control submodule the method recursively elaborates weights to control phase shifters. The method receives and transforms pairs of major operators and minor operators. The method distributes to each submodule determining its own base phase shift weight per its unique configuration.

公开(公告)号：US20160072186A1

公开(公告)日：2016-03-10

申请号：US14479352

申请日：2014-09-07

申请人： James Wang

发明人： James Wang

IPC分类号： H01Q3/34

CPC分类号： H01Q3/2605 ,  G01S3/14

摘要： An array antenna system consists of layered construct of subarrays. Each beam pointing angle requires an antenna weight vector (AWV). A circuit tracks the changing orientation of a beam within a much larger virtual array of antenna weights. A row or column of a local RAM may be determined to be least likely to be read next and is overwritten with antenna weights more likely to be read next. An address translation circuit represents the RAM as a barrel. An adaptively adjusted antenna weight method optimizes received signal power. A beam splitting method provides a mirror beam pointing direction by wrapping around a look ahead table of antenna weight vectors when an antenna is itself gyrating or when a remote transceiver is anticipated to transit the horizon.

摘要翻译： 阵列天线系统由分层构造的子阵列组成。 每个光束指向角需要一个天线权重向量（AWV）。 电路跟踪在更大的天线权重的虚拟阵列内的波束的变化方向。 本地RAM的行或列可以被确定为不太可能接下来读取，并且被更接近更可能读取的天线权重覆盖。 地址转换电路将RAM表示为桶。 自适应调节的天线权重法优化接收信号功率。 当天线本身旋转时或者当远程收发器预期到达地平线时，分束方法通过围绕天线加权矢量的前视表来提供镜射束指向方向。