公开(公告)号：US08006070B2

公开(公告)日：2011-08-23

申请号：US11951112

申请日：2007-12-05

申请人： Michael Karl Gschwind ,  Robert Alan Philhower ,  Raymond Cheung Yeung

发明人： Michael Karl Gschwind ,  Robert Alan Philhower ,  Raymond Cheung Yeung

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/3844 ,  G06F9/3802 ,  G06F9/3804

摘要： An information handling system includes a processor that throttles an instruction fetcher whenever a group of instructions in a branch instruction queue together exhibits a confidence in the accuracy of branch predictions of branch instructions therein that is less than a first predetermined threshold confidence threshold. In one embodiment, the processor includes a fetch throttle controller that inhibits fetch throttling by the instruction fetcher when confidence in the accuracy of a branch prediction for a particular currently issued branch instruction exhibits less than a second predetermined threshold confidence threshold.

摘要翻译： 信息处理系统包括处理器，其每当分支指令队列中的一组指令一起表现出对小于第一预定阈值置信阈值的分支指令的分支预测的精度的置信度时，可以节制指令获取器。 在一个实施例中，处理器包括取消节流控制器，当对当前发出的特定分支指令的分支预测的准确度的置信度小于第二预定阈值置信阈值时，该指令节省控制器禁止指令获取器的获取节流。

公开(公告)号：US07631308B2

公开(公告)日：2009-12-08

申请号：US11055850

申请日：2005-02-11

申请人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

发明人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

IPC分类号： G06F9/46

CPC分类号： G06F9/30101 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4818 ,  G06F9/485

摘要： A method is disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread.

摘要翻译： 在数据处理系统中公开了一种用于确保在每个时钟周期期间同时执行多个线程的同时多线程（SMT）微处理器中的处理公平性的方法。 在持续预期数量的时钟周期的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。 在标准选择状态期间，根据标准选择定义分配时钟周期优先级，通过在标准选择状态期间选择作为主线程的第一线程和第二线程作为次线程。 如果存在需要覆盖标准选择定义的条件，则执行超越状态，在该状态期间，通过选择第二个线程作为主线程，并将第一个线程作为次要线程来覆盖标准选择定义。

公开(公告)号：US20090193240A1

公开(公告)日：2009-07-30

申请号：US12023028

申请日：2008-01-30

申请人： Michael Karl Gschwind ,  Robert Alan Philhower ,  Raymond Cheung Yeung

发明人： Michael Karl Gschwind ,  Robert Alan Philhower ,  Raymond Cheung Yeung

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/3842

摘要： An information handling system employs a processor that includes a thread priority controller. The processor includes a memory array that stores instruction threads including branch instructions. A branch unit in the processor sends flush information to the thread priority controller when a particular branch instruction in a particular instruction thread requires a flush operation. The flush information may indicate the correctness of incorrectness of a branch prediction for the particular branch instruction and thus the necessity of a flush operation. The flush information may also include a thread ID of the particular thread. If the flush information for the particular branch instruction of the particular thread indicates that a flush operation is necessary, the thread priority controller in response speculatively increases or boosts the priority of the particular instruction thread including the particular branch instruction. In this manner, a fetcher in the processor obtains ready access to the particular thread in the memory array.

摘要翻译： 信息处理系统采用包括线程优先级控制器的处理器。 处理器包括存储包括分支指令的指令线程的存储器阵列。 当特定指令线程中的特定分支指令需要刷新操作时，处理器中的分支单元向线程优先级控制器发送刷新信息。 刷新信息可以指示特定分支指令的分支预测的不正确性的正确性，并且因此表明刷新操作的必要性。 刷新信息还可以包括特定线程的线程ID。 如果特定线程的特定分支指令的刷新信息指示需要刷新操作，则线程优先级控制器响应地推测地增加或提高包括特定分支指令的特定指令线程的优先级。 以这种方式，处理器中的提取器获得对存储器阵列中的特定线程的即时访问。

公开(公告)号：US20080294884A1

公开(公告)日：2008-11-27

申请号：US12129876

申请日：2008-05-30

申请人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

发明人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

IPC分类号： G06F9/30

CPC分类号： G06F9/30101 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4818 ,  G06F9/485

摘要： A method, apparatus, and computer program product are disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.

摘要翻译： 在数据处理系统中公开了一种方法，装置和计算机程序产品，用于确保在每个时钟周期期间同时执行多个线程的同时多线程（SMT）微处理器中的处理公平性。 在持续预期数量的时钟周期的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。 在标准选择状态期间，根据标准选择定义分配时钟周期优先级，通过在标准选择状态期间选择作为主线程的第一线程和第二线程作为次线程。 如果存在需要覆盖标准选择定义的条件，则执行超越状态，在该状态期间，通过选择第二个线程作为主线程，并将第一个线程作为次要线程来覆盖标准选择定义。 超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。 响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。

公开(公告)号：US08418180B2

公开(公告)日：2013-04-09

申请号：US12129876

申请日：2008-05-30

申请人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

发明人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

IPC分类号： G06F9/46

CPC分类号： G06F9/30101 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4818 ,  G06F9/485

摘要： A method, apparatus, and computer program product are disclosed for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles by selecting the first thread to be a primary thread and the second thread to be a secondary thread. If a condition exists that requires overriding, an override state is executed by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.

摘要翻译： 公开了一种用于确保同时多线程（SMT）微处理器中的处理公平性的方法，装置和计算机程序产品。 在通过选择作为主线程的第一线程和第二线程成为辅线程的持续期望的时钟周期数的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。 如果存在需要覆盖的条件，则通过选择作为主线程的第二个线程和第一个线程作为辅助线程来执行覆盖状态。 超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。 响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。

公开(公告)号：US07490226B2

公开(公告)日：2009-02-10

申请号：US11054289

申请日：2005-02-09

申请人： Hung Qui Le ,  Dung Quoc Nguyen ,  Raymond Cheung Yeung

发明人： Hung Qui Le ,  Dung Quoc Nguyen ,  Raymond Cheung Yeung

IPC分类号： G06F9/312

CPC分类号： G06F9/383 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3867

摘要： A method and related apparatus is provided for a processor having a number of registers, wherein instructions are sequentially issued to move through a sequence of execution stages, from an initial stage to a final write back stage. As a method, an embodiment includes the step of issuing a first instruction, such as an FMA instruction, to move through the sequence of execution stages, the first instruction being directed to a specified one of the registers. The method further includes issuing a second instruction to move through the execution stages, the second instruction being issued after the first instruction has issued, but before the first instruction reaches the final write back stage. The second instruction is likewise directed to the specified register, and comprises either a store instruction or a load instruction, selectively. R and W bits corresponding to the specified register are used to ensure that a store instruction does not read data from, and that a load instruction does not write data to the specified register, respectively, before the first instruction is moved to the final write back stage.

摘要翻译： 提供了一种用于具有多个寄存器的处理器的方法和相关装置，其中顺序地发出指令以从初始阶段到最终回写阶段移动经过一系列执行阶段。 作为一种方法，实施例包括发出诸如FMA指令的第一指令以移动经过执行级序列的步骤，第一指令被引导到指定的一个寄存器。 该方法还包括发出第二指令以移动通过执行阶段，第二指令在第一指令发出之后但在第一指令到达最终回写阶段之前发出。 第二条指令同样针对指定的寄存器，并且选择性地包括存储指令或加载指令。 使用与指定寄存器相对应的R和W位来确保存储指令不会从第一指令移动到最终回写之前分别读取数据，并且加载指令不会将数据写入指定的寄存器 阶段。

公开(公告)号：US20080256345A1

公开(公告)日：2008-10-16

申请号：US11733589

申请日：2007-04-10

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Michael Karl Gschwind ,  Ravi Nair ,  Robert Alan Philhower ,  Wolfram Sauer ,  Raymond Cheung Yeung

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Michael Karl Gschwind ,  Ravi Nair ,  Robert Alan Philhower ,  Wolfram Sauer ,  Raymond Cheung Yeung

IPC分类号： G06F7/38

CPC分类号： G06F9/3844 ,  G06F1/3203 ,  G06F9/3802 ,  G06F9/3806

摘要： An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions.

摘要翻译： 一种信息处理系统包括处理器，每当对分支指令队列中存储的分支指令的分支预测中的不准确性或缺乏置信度的不准确性或缺乏置信度超过预定的不准确度或误差的阈值置信水平时，可以节制指令获取器。 以这种方式，当处理器可能会错误地预测分支指令的结果时，获取操作减慢以节省处理器功率。 当处理器可能正确预测分支指令的结果时，获取操作将返回全速。

公开(公告)号：US07380104B2

公开(公告)日：2008-05-27

申请号：US11380078

申请日：2006-04-25

申请人： William Elton Burky ,  Raymond Cheung Yeung

发明人： William Elton Burky ,  Raymond Cheung Yeung

IPC分类号： G06F9/30 ,  G06F9/40

CPC分类号： G06F9/3836 ,  G06F9/3838

摘要： A method is provided for evaluating two or more instructions in an out of order issue queue during a particular cycle of the queue, to select an instruction for issue during the next following cycle. If an instruction was previously designated to issue during the particular cycle, one or more instructions in the queue are evaluated to determine if any of them are dependent on the designated instruction. For the evaluation, each instruction placed into the queue is accompanied by corresponding logic elements that provide destination to source compares for the instruction. In an embodiment comprising a method, the oldest ready instruction in the queue during a particular cycle is identified. When an instruction was previously designated to issue during the particular cycle, it is determined whether at least a first instruction in the queue complies with each condition in a set of conditions, the set including at least the conditions that the first instruction has a dependency on the designated instruction, and that the first instruction is older than the oldest ready instruction. The first instruction is selected for issue during the next following cycle only if the first instruction complies with each condition in the set.

摘要翻译： 提供了一种用于在队列的特定周期期间评估出故障发送队列中的两个或更多个指令的方法，以在下一个后续周期中选择要发出的指令。 如果先前指定在特定周期内发出指令，则会对队列中的一个或多个指令进行评估，以确定其中任何一个是否依赖于指定的指令。 对于评估，放置到队列中的每条指令都伴随有相应的逻辑元素，为指令提供目标到源的比较。 在包括方法的实施例中，识别在特定周期期间队列中最早的就绪指令。 当先前指定在特定周期期间发出指令时，确定队列中的至少第一指令是否符合一组条件中的每个条件，该集合至少包括第一指令依赖于的条件 指定的指令，并且第一条指令比最早的就绪指令更旧。 仅当第一条指令符合该组中的每个条件时，才在下一个后续周期中选择第一条指令进行发布。

公开(公告)号：US07000047B2

公开(公告)日：2006-02-14

申请号：US10422036

申请日：2003-04-23

申请人： Dung Quoc Nguyen ,  Raymond Cheung Yeung

发明人： Dung Quoc Nguyen ,  Raymond Cheung Yeung

IPC分类号： G06F12/00 ,  G06F12/14 ,  G06F15/16 ,  G06F9/46

CPC分类号： G06F9/3017 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861

摘要： A method and multithreaded processor for handling livelocks in a simultaneous multithreaded processor. A number of instructions for a thread in a queue may be counted. A counter in the queue may be incremented if the number of instructions for the thread in the queue in a previous clock cycle is equal to the number of instructions for the thread in the queue in a current clock cycle. If the value of the counter equals a threshold value, then a livelock condition may be detected. Further, if the value of the counter equals a threshold value, a recovery action may be activated to handle the livelock condition detected. The recovery action may include blocking the instructions associated with a thread causing the livelock condition from being executed thereby ensuring that the locked thread makes forward progress.

摘要翻译： 一种用于处理同时多线程处理器中的活动锁的方法和多线程处理器。 可以对队列中的线程的许多指令进行计数。 如果先前时钟周期中队列中的线程的指令数目等于当前时钟周期中队列中线程的指令数，队列中的计数器可能会增加。 如果计数器的值等于阈值，则可以检测到活动锁定状态。 此外，如果计数器的值等于阈值，则可以激活恢复动作来处理检测到的活动锁定状态。 恢复动作可以包括阻止与线程相关联的指令，导致活动锁定条件被执行，从而确保锁定的线程前进进行。

公开(公告)号：US08255669B2

公开(公告)日：2012-08-28

申请号：US12023004

申请日：2008-01-30

申请人： Michael Karl Gschwind ,  Robert Alan Philhower ,  Raymond Cheung Yeung

发明人： Michael Karl Gschwind ,  Robert Alan Philhower ,  Raymond Cheung Yeung

IPC分类号： G06F9/32

CPC分类号： G06F9/3851 ,  G06F9/3804 ,  G06F9/3844 ,  G06F9/3861

摘要： An information handling system employs a processor that includes a thread priority controller. An issue unit in the processor sends branch issue information to the thread priority controller when a branch instruction of an instruction thread issues. In one embodiment, if the branch issue information indicates low confidence in a branch prediction for the branch instruction, the thread priority controller speculatively increases or boosts the priority of the instruction thread containing this low confidence branch instruction. In the manner, should a branch redirect actually occur due to a mispredict, a fetcher is ready to access a redirect address in a memory array sooner than would otherwise be possible.

摘要翻译： 信息处理系统采用包括线程优先级控制器的处理器。 当指令线程的分支指令发生时，处理器中的问题单元向线程优先级控制器发送分支发出信息。 在一个实施例中，如果分支发布信息在分支指令的分支预测中表示低置信度，则线程优先级控制器推测地增加或提高包含该低置信度分支指令的指令线程的优先级。 以这种方式，如果分支重定向实际上由于错误的预测而发生，则提取器准备好比存储器阵列更快地访问存储器阵列中的重定向地址。