公开(公告)号：US20090072319A1

公开(公告)日：2009-03-19

申请号：US11917608

申请日：2006-06-14

申请人： Jan Sonsky ,  Anco Heringa

发明人： Jan Sonsky ,  Anco Heringa

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7824 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0886 ,  H01L29/7835 ,  H01L29/78624 ,  H01L29/861

摘要： A semiconductor device includes at least one active component (18) having a p-n junction (26) on the semiconductor substrate in an active region (19) of the semiconductor substrate (4). A shallow trench isolation pattern is used to form a plurality of longitudinally extending shallow trenches (12) containing insulator (14). These trenches define a plurality of longitudinal active stripes (10) between the shallow trenches (12). The shallow trench isolation depth (dsπ) is greater than the junction depth (dsO of the longitudinal active stripes and the width (wsO of the active stripes (10) is less than the depletion length (ldepi) of the p-n junction.

摘要翻译： 半导体器件包括在半导体衬底（4）的有源区（19）中的半导体衬底上具有p-n结（26）的至少一个有源元件（18）。 浅沟槽隔离图案用于形成包含绝缘体（14）的多个纵向延伸的浅沟槽（12）。 这些沟槽在浅沟槽（12）之间限定多个纵向有源条纹（10）。 浅沟槽隔离深度（dspi）大于结深度（纵向有源条纹的dsO）和有源条纹（10）的宽度（wsO）小于p-n结的耗尽长度（ldepi）。

公开(公告)号：US08541267B2

公开(公告)日：2013-09-24

申请号：US12933414

申请日：2009-03-20

申请人： Jan Sonsky ,  Anco Heringa

发明人： Jan Sonsky ,  Anco Heringa

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L29/66

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： The present invention relates to a method for fabricating a FinFET on a substrate. The method comprises providing a substrate with an active semiconductor layer on an insulator layer, and concurrently fabricating trench isolation regions in the active semiconductor layer for electrically isolating different active regions in the active semiconductor layer from each other, and trench gate-isolation regions in the active semiconductor layer for electrically isolating at least one gate region of the FinFET in the active semiconductor layer from a fin-shaped channel region of the FinFET in the active semiconductor layer.

摘要翻译： 本发明涉及一种在衬底上制造FinFET的方法。 该方法包括在绝缘体层上提供具有有源半导体层的衬底，并且同时制造有源半导体层中的沟槽隔离区，用于将有源半导体层中的不同有源区彼此电隔离，以及沟槽栅极隔离区 有源半导体层，用于将有源半导体层中的FinFET的至少一个栅极区域与有源半导体层中的FinFET的鳍状沟道区电隔离。

公开(公告)号：US08390077B2

公开(公告)日：2013-03-05

申请号：US13561710

申请日：2012-07-30

申请人： Jan Sonsky ,  Anco Heringa

发明人： Jan Sonsky ,  Anco Heringa

IPC分类号： H01L27/088

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823493

摘要： A semiconductor device includes a semiconductor substrate having a first portion and a second portion and a first transistor of a first type formed in the first portion of the substrate, the first transistor being operable at a first voltage, and the first transistor including a doped channel region of a second type opposite of the first type. The semiconductor device also includes a second transistor of the second type formed in the second portion of the substrate, the second transistor being operable at a second voltage greater than the first voltage, the second transistor including an extended doped feature of the second type. Further, the semiconductor device includes a well of the first type in the semiconductor substrate under a gate of the second transistor, wherein the well does not extend directly under the extended doped feature and the extended doped feature does not extend directly under the well.

摘要翻译： 半导体器件包括具有第一部分和第二部分的半导体衬底和形成在衬底的第一部分中的第一类型的第一晶体管，第一晶体管可在第一电压下操作，并且第一晶体管包括掺杂沟道 与第一类型相反的第二类型的区域。 半导体器件还包括形成在衬底的第二部分中的第二类型的第二晶体管，第二晶体管可操作在大于第一电压的第二电压，第二晶体管包括第二类型的延伸掺杂特征。 此外，半导体器件包括在第二晶体管的栅极下的半导体衬底中的第一类型的阱，其中阱不直接在扩展掺杂特征下延伸，并且扩展掺杂特征不直接在阱下面延伸。

公开(公告)号：US08373227B2

公开(公告)日：2013-02-12

申请号：US13124219

申请日：2009-10-06

申请人： Jan Sonsky ,  Anco Heringa

发明人： Jan Sonsky ,  Anco Heringa

IPC分类号： H01L29/66 ,  H01L21/76

CPC分类号： H01L29/7835 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/66659

摘要： A semiconductor device comprises a substrate including a first region and a second region of a first conductivity type and a third region between the first and second regions of a second conductivity type opposite to the first conductivity type, and being covered by a dielectric layer. A plurality of trenches laterally extend between the third and second region, are filled with an insulating material, and are separated by active stripes with a doping profile having a depth not exceeding the depth of the trenches wherein each trench terminates before reaching the dielectric layer and is separated from the third region by a substrate portion such that the respective boundaries between the substrate portions and the trenches are not covered by the dielectric layer. A method for manufacturing such a semiconductor device is also disclosed.

摘要翻译： 一种半导体器件包括：衬底，其包括第一导电类型的第一区域和第二区域，以及位于与第一导电类型相反的第二导电类型的第一和第二区域之间并被电介质层覆盖的第三区域。 在第三和第二区域之间横向延伸的多个沟槽被绝缘材料填充，并且被具有深度不超过沟槽深度的掺杂分布的有源条带分离，其中每个沟槽在到达介电层之前终止， 通过衬底部分与第三区域分离，使得衬底部分和沟槽之间的相应边界不被电介质层覆盖。 还公开了一种制造这种半导体器件的方法。

公开(公告)号：US20110006369A1

公开(公告)日：2011-01-13

申请号：US12933414

申请日：2009-03-20

申请人： Jan Sonsky ,  Anco Heringa

发明人： Jan Sonsky ,  Anco Heringa

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： The present invention relates to a method for fabricating a FinFET on a substrate. The method comprises providing a substrate with an active semiconductor layer on an insulator layer, and concurrently fabricating trench isolation regions in the active semiconductor layer for electrically isolating different active regions in the active semiconductor layer from each other, and trench gate-isolation regions in the active semiconductor layer for electrically isolating at least one gate region of the FinFET in the active semiconductor layer from a fin-shaped channel region of the FinFET in the active semiconductor layer.

摘要翻译： 本发明涉及一种在衬底上制造FinFET的方法。 该方法包括在绝缘体层上提供具有有源半导体层的衬底，并且同时制造有源半导体层中的沟槽隔离区，用于将有源半导体层中的不同有源区彼此电隔离，以及沟槽栅极隔离区 有源半导体层，用于将有源半导体层中的FinFET的至少一个栅极区域与有源半导体层中的FinFET的鳍状沟道区电隔离。

公开(公告)号：US07808050B2

公开(公告)日：2010-10-05

申请号：US11917608

申请日：2006-06-14

申请人： Jan Sonsky ,  Anco Heringa

发明人： Jan Sonsky ,  Anco Heringa

IPC分类号： H01L21/76 ,  H01L29/78

CPC分类号： H01L29/7824 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0886 ,  H01L29/7835 ,  H01L29/78624 ,  H01L29/861

摘要： A semiconductor device includes at least one active component (18) having a p-n junction (26) on the semiconductor substrate in an active region (19) of the semiconductor substrate (4). A shallow trench isolation pattern is used to form a plurality of longitudinally extending shallow trenches (12) containing insulator (14). These trenches define a plurality of longitudinal active stripes (10) between the shallow trenches (12). The shallow trench isolation depth (dsπ) is greater than the junction depth (dsO of the longitudinal active stripes and the width (wsO of the active stripes (10) is less than the depletion length (ldepi) of the p-n junction.

摘要翻译： 半导体器件包括在半导体衬底（4）的有源区（19）中的半导体衬底上具有p-n结（26）的至少一个有源元件（18）。 浅沟槽隔离图案用于形成包含绝缘体（14）的多个纵向延伸的浅沟槽（12）。 这些沟槽在浅沟槽（12）之间限定多个纵向有源条纹（10）。 浅沟槽隔离深度（ds＆pgr）大于结深度（纵向有源条纹的dsO）和有源条纹（10）的宽度（wsO）小于p-n结的耗尽长度（ldepi）。

公开(公告)号：US20120299112A1

公开(公告)日：2012-11-29

申请号：US13561710

申请日：2012-07-30

申请人： Jan Sonsky ,  Anco Heringa

发明人： Jan Sonsky ,  Anco Heringa

IPC分类号： H01L27/092

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823493

摘要： A semiconductor device includes a semiconductor substrate having a first portion and a second portion and a first transistor of a first type formed in the first portion of the substrate, the first transistor being operable at a first voltage, and the first transistor including a doped channel region of a second type opposite of the first type. The semiconductor device also includes a second transistor of the second type formed in the second portion of the substrate, the second transistor being operable at a second voltage greater than the first voltage, the second transistor including an extended doped feature of the second type. Further, the semiconductor device includes a well of the first type in the semiconductor substrate under a gate of the second transistor, wherein the well does not extend directly under the extended doped feature and the extended doped feature does not extend directly under the well.

摘要翻译： 半导体器件包括具有第一部分和第二部分的半导体衬底和形成在衬底的第一部分中的第一类型的第一晶体管，第一晶体管可在第一电压下操作，并且第一晶体管包括掺杂沟道 与第一类型相反的第二类型的区域。 半导体器件还包括形成在衬底的第二部分中的第二类型的第二晶体管，第二晶体管可操作在大于第一电压的第二电压，第二晶体管包括第二类型的延伸掺杂特征。 此外，半导体器件包括在第二晶体管的栅极下的半导体衬底中的第一类型的阱，其中阱不直接在扩展掺杂特征下延伸，并且扩展掺杂特征不直接在阱下面延伸。

公开(公告)号：US08247280B2

公开(公告)日：2012-08-21

申请号：US12582334

申请日：2009-10-20

申请人： Jan Sonsky ,  Anco Heringa

发明人： Jan Sonsky ,  Anco Heringa

IPC分类号： H01L21/8238

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823493

摘要： A method of fabricating a semiconductor device is provided that includes providing a semiconductor substrate having a first portion and a second portion, forming a first transistor in the first portion of the substrate, the first transistor being operable at a first voltage, and forming a second transistor in the second portion of the substrate, the second transistor being operable at a second voltage greater than the first voltage. The formation of the second transistor includes forming an extended feature of the second transistor with a photomask that is used to adjust a threshold voltage of the first transistor.

摘要翻译： 提供一种制造半导体器件的方法，其包括提供具有第一部分和第二部分的半导体衬底，在衬底的第一部分中形成第一晶体管，第一晶体管可在第一电压下工作，并形成第二晶体管 晶体管在基板的第二部分中，第二晶体管可操作在大于第一电压的第二电压。 第二晶体管的形成包括用用于调节第一晶体管的阈值电压的光掩模形成第二晶体管的扩展特征。

公开(公告)号：US20110198691A1

公开(公告)日：2011-08-18

申请号：US13124219

申请日：2009-10-06

申请人： Jan Sonsky ,  Anco Heringa

发明人： Jan Sonsky ,  Anco Heringa

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7835 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/66659

摘要： A semiconductor device eg. a MOSFET (1) comprising a substrate (40) including a first region (18) and a second region (16) of a first conductivity type and a third region (42) between the first and second regions of a type opposite to the first conductivity type, and being covered by a dielectric layer (20), a plurality of trenches (12) laterally extending between the third and second region, said trenches being filled with an insulating material, and being separated by active stripes (14) comprising a doping profile having a depth not exceeding the depth of the trenches wherein each trench terminates before reaching the dielectric layer (20),namely is separated from the third region by a substrate portion (26) such that the respective boundaries between the substrate portions and the trenches are not covered by the dielectric layer. A method for manufacturing such a semiconductor device is also disclosed.

摘要翻译： 半导体器件例如 包括基板（40）的MOSFET（1），所述基板（40）包括第一导电类型的第一区域（18）和第二区域（16）和位于第一和第二区域之间的第三区域 导电类型，并被介电层（20）覆盖，在第三和第二区域之间横向延伸的多个沟槽（12），所述沟槽填充有绝缘材料，并且由有源条纹（14）分离，包括 掺杂分布具有不超过沟槽深度的深度，其中每个沟槽在到达电介质层（20）之前终止，即通过衬底部分（26）从第三区域分离，使得衬底部分和 沟槽不被电介质层覆盖。 还公开了一种用于制造这种半导体器件的方法。

公开(公告)号：US20110089498A1

公开(公告)日：2011-04-21

申请号：US12582334

申请日：2009-10-20

申请人： Jan Sonsky ,  Anco Heringa

发明人： Jan Sonsky ,  Anco Heringa

IPC分类号： H01L27/088 ,  H01L21/8238 ,  H01L21/8234

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823493

摘要： A method of fabricating a semiconductor device is provided that includes providing a semiconductor substrate having a first portion and a second portion, forming a first transistor in the first portion of the substrate, the first transistor being operable at a first voltage, and forming a second transistor in the second portion of the substrate, the second transistor being operable at a second voltage greater than the first voltage. The formation of the second transistor includes forming an extended feature of the second transistor with a photomask that is used to adjust a threshold voltage of the first transistor.

摘要翻译： 提供一种制造半导体器件的方法，其包括提供具有第一部分和第二部分的半导体衬底，在衬底的第一部分中形成第一晶体管，第一晶体管可在第一电压下工作，并形成第二晶体管 晶体管在基板的第二部分中，第二晶体管可操作在大于第一电压的第二电压。 第二晶体管的形成包括用用于调节第一晶体管的阈值电压的光掩模形成第二晶体管的扩展特征。