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    Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process
    3.
    发明授权
    Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process 有权
    使用多台板化学机械抛光（CMP）工艺形成铜互连的方法

    公开(公告)号：US06274478B1

    公开(公告)日：2001-08-14

    申请号：US09352136

    申请日：1999-07-13

    申请人： Janos Farkas ,  Brian G. Anthony ,  Abbas Guvenilir ,  Mohammed Rabiul Islam ,  Venkat Kolagunta ,  John Mendonca ,  Rajesh Tiwari ,  Suresh Venkatesan

    发明人： Janos Farkas ,  Brian G. Anthony ,  Abbas Guvenilir ,  Mohammed Rabiul Islam ,  Venkat Kolagunta ,  John Mendonca ,  Rajesh Tiwari ,  Suresh Venkatesan

    IPC分类号： H01L214763

    CPC分类号： H01L21/7684 ,  H01L21/02074 ,  H01L21/31053 ,  H01L21/3212

    摘要： A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scrubber.

    摘要翻译： 铜互连抛光工艺通过使用第一压板抛光（17）铜（63）的体积厚度开始。 然后使用第二压板来去除（19）薄的剩余界面铜层以暴露阻挡膜（61）。 计算机控制（21）监测第一和第二压板的抛光时间并调整这些时间以提高晶片的吞吐量。 一个或多个压板和/或晶片在界面铜抛光剂和阻隔抛光剂之间漂洗（20），以减少淤浆交叉污染。 然后使用第三压板和浆料抛光掉屏障（61）的暴露部分以完成铜互连结构的抛光。 使用含有防腐蚀液体的储存罐将晶片排队，直到后续的擦洗操作（25）。 使用基本上无光的擦洗操作（25）用于减少洗涤器的干燥室中的铜的光伏诱发的腐蚀。

    Method for forming a dual inlaid copper interconnect structure
    4.
    发明授权
    Method for forming a dual inlaid copper interconnect structure 有权
    用于形成双嵌入铜互连结构的方法

    公开(公告)号：US06326301B1

    公开(公告)日：2001-12-04

    申请号：US09352134

    申请日：1999-07-13

    申请人： Suresh Venkatesan ,  Bradley P. Smith ,  Mohammed Rabiul Islam

    发明人： Suresh Venkatesan ,  Bradley P. Smith ,  Mohammed Rabiul Islam

    IPC分类号： H01L214763

    CPC分类号： H01L21/76834 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76832 ,  Y10S438/97

    摘要： A dual inlaid copper interconnect structure uses a plasma enhanced nitride (PEN) bottom capping layer and a silicon rich silicon oxynitride intermediate etch stop layer. The interfaces (16a, 16b, 20a, and 20b) between these layers (16 and 20) and their adjacent dielectric layers (18 and 22) are positioned in the stack (13) independent of the desired aspect ratio of trench openings of the copper interconnect in order to improve optical properties of the dielectric stack (13). Etch processing is then used to position the layers (16) and (20) at locations within the inlaid structure depth that result in one or more of reduced DC leakage current, improved optical performance, higher frequency of operation, reduced cross talk, increased flexibility of design, or like improvements.

    摘要翻译： 双嵌入铜互连结构使用等离子体增强氮化物（PEN）底盖层和富硅氧氮化硅中间蚀刻停止层。 这些层（16和20）及其相邻的电介质层（18和22）之间的界面（16a，16b，20a和20b）位于堆叠（13）中，与铜的沟槽开口的所需纵横比无关 互连以改善电介质堆叠（13）的光学性质。 然后使用蚀刻处理将层（16）和（20）定位在镶嵌结构深度内的位置，导致一个或多个减小的DC泄漏电流，改进的光学性能，更高的操作频率，减少的串扰，增加的灵活性 的设计，或类似的改进。