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公开(公告)号：US06297155B1
公开(公告)日：2001-10-02
申请号：US09305093
申请日：1999-05-03
申请人： Cindy Reidsema Simpson , Robert Douglas Mikkola , Matthew T. Herrick , Brett Caroline Baker , David Moralez Pena , Edward Acosta , Rina Chowdhury , Marijean Azrak , Cindy Kay Goldberg , Mohammed Rabiul Islam
发明人： Cindy Reidsema Simpson , Robert Douglas Mikkola , Matthew T. Herrick , Brett Caroline Baker , David Moralez Pena , Edward Acosta , Rina Chowdhury , Marijean Azrak , Cindy Kay Goldberg , Mohammed Rabiul Islam
IPC分类号： H01L2144
CPC分类号： H01L21/76877 , H01L21/2885
摘要： A method for electroplating a copper layer (118) over a wafer (20) powers a cathode of an electroplating system (10) in a manner that obtains improved copper interconnects. A control system (34) powers the cathode of the system (10) with a mix of two or more of: (i) positive low-powered DC cycles (201 or 254); (ii) positive high-powered DC cycles (256 or 310); (iii) low-powered, pulsed, positive-power cycles (306 or 530); (iv) high-powered, pulsed, positive-powered cycles (212, 252, 302, or 352); and/or (v) negative pulsed cycles (214, 304, 510, 528, or 532). The collection of these cycles functions to electroplate copper or a like metal (118) onto the wafer (20). During electroplating, insitu process control and/or endpointing (506, 512, or 520) is performed to further improve the resulting copper interconnect.
摘要翻译： 在晶片（20）上电镀铜层（118）的方法以获得改进的铜互连的方式为电镀系统（10）的阴极供电。 控制系统（34）以下列两种或多种的混合来为系统（10）的阴极供电：（i）正低功率DC循环（201或254）; （ii）正极大功率直流循环（256或310）; （iii）低功率，脉冲，正功率周期（306或530）; （iv）高功率，脉冲，正动力循环（212,252,302或352）; 和/或（v）负脉冲循环（214,304,510,528或532）。 这些循环的收集用于将铜或类似金属（118）电镀到晶片（20）上。 在电镀期间，执行基底过程控制和/或终点（506,512或520）以进一步改善所得铜互连。
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公开(公告)号：US07323094B2
公开(公告)日：2008-01-29
申请号：US10218810
申请日：2002-08-14
CPC分类号： H01L21/2885 , C25D3/665 , C25D5/00 , C25D5/04 , C25D5/18 , C25D7/123 , C25D17/001 , C25D17/008 , C25D21/00 , Y10S204/07
摘要： An electroplating system (30) and process makes electrical current density across a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that plates on electrical current density modifier portions (364) of structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.
摘要翻译： 电镀系统（30）和工艺使得在电镀期间半导体器件衬底（20）表面上的电流密度更均匀，以允许更均匀或定制的导电材料沉积。 电流密度调节剂（364和37）降低了衬底（20）边缘附近的电流密度。 通过降低衬底（20）边缘附近的电流密度，电镀变得更均匀或可以被调整，使得在衬底（20）的中心附近有更多的材料被镀敷。 该系统也可以被修改，使得可以去除在结构（36）的电流密度调节部分（364）上的材料，而不必拆卸头部（35）的任何部分或以其他方式从结构（36）移除结构 系统。 这种原位清洗可减少设备停机时间，增加设备使用寿命，并减少颗粒数量。
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公开(公告)号：US06500324B1
公开(公告)日：2002-12-31
申请号：US09561776
申请日：2000-05-01
IPC分类号： C25D712
CPC分类号： H01L21/2885 , C25D3/665 , C25D5/00 , C25D5/04 , C25D5/18 , C25D7/123 , C25D17/001 , C25D17/008 , C25D21/00 , Y10S204/07
摘要： An electroplating system (30) and process makes electrical current density across, a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that electrical current density modifier portions (364) on structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.
摘要翻译： 电镀系统（30）和工艺使电流密度跨过半导体器件衬底（20）表面在电镀期间更均匀，以允许更均匀或定制的导电材料沉积。 电流密度调节剂（364和37）降低了衬底（20）边缘附近的电流密度。 通过降低衬底（20）边缘附近的电流密度，电镀变得更均匀或可以被调整，使得在衬底（20）的中心附近有更多的材料被镀敷。 该系统也可以被修改，使得可以去除结构（36）上的电流密度调节部分（364）的材料，而不必拆卸头部（35）的任何部分或以其他方式从系统中移除结构（36） 。 这种原位清洗可减少设备停机时间，增加设备使用寿命，并减少颗粒数量。
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公开(公告)号：US06174425B1
公开(公告)日：2001-01-16
申请号：US08856459
申请日：1997-05-14
IPC分类号： C25D1706
CPC分类号： H01L21/2885 , C25D3/665 , C25D5/00 , C25D5/04 , C25D5/18 , C25D7/123 , C25D17/001 , C25D17/008 , C25D21/00 , Y10S204/07
摘要： An electroplating system (30) and process makes electrical current density across a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that electrical current density modifier portions (364) on structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.
摘要翻译： 电镀系统（30）和工艺使得在电镀期间半导体器件衬底（20）表面上的电流密度更均匀，以允许更均匀或定制的导电材料沉积。 电流密度调节剂（364和37）降低了衬底（20）边缘附近的电流密度。 通过降低衬底（20）边缘附近的电流密度，电镀变得更均匀或可以被调整，使得在衬底（20）的中心附近有更多的材料被镀敷。 该系统也可以被修改，使得可以去除结构（36）上的电流密度调节部分（364）的材料，而不必拆卸头部（35）的任何部分或以其他方式从系统中移除结构（36） 。 这种原位清洗可减少设备停机时间，增加设备使用寿命，并减少颗粒数量。
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公开(公告)号：US07838363B2
公开(公告)日：2010-11-23
申请号：US11931376
申请日：2007-10-31
IPC分类号： H01L21/00
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/42348 , H01L29/66825 , H01L29/66833
摘要： A method forms a split gate memory cell by providing a semiconductor substrate and forming an overlying select gate. The select gate has a predetermined height and is electrically insulated from the semiconductor substrate. A charge storing layer is subsequently formed overlying and adjacent to the select gate. A control gate is subsequently formed adjacent to and separated from the select gate by the charge storing layer. The charge storing layer is also positioned between the control gate and the semiconductor substrate. The control gate initially has a height greater than the predetermined height of the select gate. The control gate is recessed to a control gate height that is less than the predetermined height of the select gate. A source and a drain are formed in the semiconductor substrate.
摘要翻译： 一种方法通过提供半导体衬底并形成覆盖选择栅极形成分离栅极存储单元。 选择栅极具有预定的高度并且与半导体衬底电绝缘。 随后形成电荷存储层，覆盖并邻近选择栅极。 随后通过电荷存储层形成与选择栅极相邻并分离的控制栅极。 电荷存储层也位于控制栅极和半导体衬底之间。 控制门最初具有高于选择门的预定高度的高度。 控制栅极凹入到小于选择栅极的预定高度的控制栅极高度。 源极和漏极形成在半导体衬底中。
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公开(公告)号：US20090142895A1
公开(公告)日：2009-06-04
申请号：US11948209
申请日：2007-11-30
IPC分类号： H01L21/8234
CPC分类号： H01L21/823871 , H01L21/76897 , H01L21/823468 , H01L21/823475 , H01L29/665
摘要： A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region.
摘要翻译： 形成通孔的方法包括在半导体衬底上形成栅电极，在与栅电极相邻的半导体衬底中形成源极/漏极区域，在源/漏区域中形成硅化物区域，形成邻近硅化物间隔区 在形成硅化物区域之后形成栅电极，在栅电极，硅化物间隔物和硅化物区域之上形成层间电介质层，并且在层间电介质层中形成延伸到硅化物区域的导电通孔。
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公开(公告)号：US08173505B2
公开(公告)日：2012-05-08
申请号：US12254331
申请日：2008-10-20
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L27/11526 , H01L27/11536 , H01L27/11543 , H01L27/11573 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A method includes forming a first layer of gate material over a semiconductor substrate; forming a hard mask layer over the first layer; forming an opening; forming a charge storage layer over the hard mask layer and within the opening; forming a second layer of gate material over the charge storage layer; removing a portion of the second layer and a portion of the charge storage layer which overlie the hard mask layer, wherein a second portion of the second layer remains within the opening; forming a patterned masking layer over the hard mask layer and over the second portion, wherein the patterned masking layer defines both a first and second bitcell; and forming the first and second bitcell using the patterned masking layer, wherein each of the first and second bitcell comprises a select gate made from the first layer and a control gate made from the second layer.
摘要翻译： 一种方法包括在半导体衬底上形成栅极材料的第一层; 在第一层上形成硬掩模层; 形成开口 在所述硬掩模层和所述开口内形成电荷存储层; 在所述电荷存储层上形成栅极材料的第二层; 去除所述第二层的一部分和所述电荷存储层的覆盖所述硬掩模层的部分，其中所述第二层的第二部分保留在所述开口内; 在所述硬掩模层上并在所述第二部分上形成图案化掩模层，其中所述图案化掩模层限定第一和第二位单元; 以及使用所述图案化掩模层形成所述第一和第二位单元，其中所述第一和第二位单元中的每一个包含由所述第一层制成的选择栅极和由所述第二层制成的控制栅极。
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公开(公告)号：US20090111229A1
公开(公告)日：2009-04-30
申请号：US11931376
申请日：2007-10-31
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/42348 , H01L29/66825 , H01L29/66833
摘要： A method forms a split gate memory cell by providing a semiconductor substrate and forming an overlying select gate. The select gate has a predetermined height and is electrically insulated from the semiconductor substrate. A charge storing layer is subsequently formed overlying and adjacent to the select gate. A control gate is subsequently formed adjacent to and separated from the select gate by the charge storing layer. The charge storing layer is also positioned between the control gate and the semiconductor substrate. The control gate initially has a height greater than the predetermined height of the select gate. The control gate is recessed to a control gate height that is less than the predetermined height of the select gate. A source and a drain are formed in the semiconductor substrate.
摘要翻译： 一种方法通过提供半导体衬底并形成覆盖选择栅极形成分离栅极存储单元。 选择栅极具有预定的高度并且与半导体衬底电绝缘。 随后形成电荷存储层，覆盖并邻近选择栅极。 随后通过电荷存储层形成与选择栅极相邻并分离的控制栅极。 电荷存储层也位于控制栅极和半导体衬底之间。 控制门最初具有高于选择门的预定高度的高度。 控制栅极凹入到小于选择栅极的预定高度的控制栅极高度。 源极和漏极形成在半导体衬底中。
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公开(公告)号：US07416945B1
公开(公告)日：2008-08-26
申请号：US11676403
申请日：2007-02-19
申请人： Ramachandran Muralidhar , Rajesh A. Rao , Matthew T. Herrick , Narayanan C. Ramani , Robert F. Steimle
发明人： Ramachandran Muralidhar , Rajesh A. Rao , Matthew T. Herrick , Narayanan C. Ramani , Robert F. Steimle
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521
摘要： A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters.
摘要翻译： 一种方法形成分离栅极存储器件。 将衬底上的选择栅极材料层图案化以形成第一侧壁。 邻近第一侧壁形成牺牲隔离物。 纳米团簇形成在包括在牺牲间隔物上的衬底上。 在形成纳米团簇层之后去除牺牲隔离物，其中除去在牺牲隔离物上形成的纳米团簇并保留其他纳米团簇。 在除去牺牲间隔物之后，在衬底上形成一层控制栅极材料。 分离栅极存储器件的控制栅极由控制栅极材料层形成，其中控制栅极位于剩余的纳米簇上。
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公开(公告)号：US07745298B2
公开(公告)日：2010-06-29
申请号：US11948209
申请日：2007-11-30
IPC分类号： H01L21/336
CPC分类号： H01L21/823871 , H01L21/76897 , H01L21/823468 , H01L21/823475 , H01L29/665
摘要： A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region.
摘要翻译： 形成通孔的方法包括在半导体衬底上形成栅电极，在与栅电极相邻的半导体衬底中形成源极/漏极区域，在源/漏区域中形成硅化物区域，形成邻近硅化物间隔区 在形成硅化物区域之后形成栅电极，在栅电极，硅化物间隔物和硅化物区域之上形成层间电介质层，并且在层间电介质层中形成延伸到硅化物区域的导电通孔。
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