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公开(公告)号：US07856609B2
公开(公告)日：2010-12-21
申请号：US12164781
申请日：2008-06-30
申请人： Jason R. Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
发明人： Jason R. Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
CPC分类号： G06F17/504
摘要： A method for generating a constraint for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N′) of the netlist. A space state (S′) is created by enumerating the states of N′ from which the identified target may be asserted. A constraint space C′ is then derived from the state space S′, where C′ is the logical complement of S′. The process is repeated for multiple selected targets and the constraint spaces from each iteration are logically ANDed. Creating an overapproximate abstraction may include replacing a sequential gate with a random gate. Identifying a sequential gate may include selecting a target in the netlist, performing underapproximate verification of the target, and, if a spurious failure occurs, selecting a gate further down the fanin chain of the currently selected gate.
摘要翻译： 用于生成用于生成用于集成电路设计的验证的约束的约束的方法包括识别所述设计的网表（N）中的目标并且创建所述网表的过近似抽象（N'）。 通过枚举从其识别出的目标可以被断言的N'的状态来创建空间状态（S'）。 然后从状态空间S'导出约束空间C'，其中C'是S'的逻辑补码。 对于多个选定的目标重复该过程，并且来自每个迭代的约束空间被逻辑地进行AND。 创建过近似抽象可能包括用随机门替换顺序门。 识别顺序门可以包括选择网表中的目标，执行目标的近似不正确的验证，并且如果发生虚假故障，则选择进一步向下沿当前选择的门的扇形链的门。
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2.发明授权Computer program product for verification using reachability overapproximation 失效使用可达性过近似的验证计算机程序产品公开(公告)号：US07788615B2
公开(公告)日：2010-08-31
申请号：US11938612
申请日：2007-11-12
CPC分类号： G06F17/504
摘要： A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is expanded to create a superset of the first initial state containing one or more states reachable from the first initial state of the design. A superset is synthesized to define a second initial state of the design. Application of the superset to the design is overapproximated through cutpoint insertion into the superset to obtain a modified superset, and the property is verified with reference to the modified superset.
摘要翻译： 公开了一种用于验证设计符合期望属性的方法，系统和计算机程序产品。 该方法包括接收设计，设计的第一初始状态和关于设计的验证的属性。 设计的第一初始状态被扩展以创建包含从设计的第一初始状态可访问的一个或多个状态的第一初始状态的超集。 合成超集以定义设计的第二初始状态。 超设计对设计的应用通过将切入点插入到超集中来获得修改后的超集，并且参考修改后的超集来验证该属性。
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公开(公告)号：US07421669B2
公开(公告)日：2008-09-02
申请号：US11236451
申请日：2005-09-27
CPC分类号： G06F17/504
摘要： A method for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N′) of the netlist. A space state (S′) is created by enumerating the states of N′ from which the identified target may be asserted. A constraint space C′ is then derived from the state space S′, where C′ is the logical complement of S′. The process is repeated for multiple selected targets and the constraint spaces from each iteration are logically ANDed. Creating an overapproximate abstraction may include replacing a sequential gate with a random gate. Identifying a sequential gate may include selecting a target in the netlist, performing underapproximate verification of the target, and, if a spurious failure occurs, selecting a gate further down the fanin chain of the currently selected gate.
摘要翻译： 一种用于生成用于验证集成电路设计的约束的方法包括识别设计的网表（N）中的目标并创建网表的过近似抽象（N'）。 通过枚举从其识别出的目标可以被断言的N'的状态来创建空间状态（S'）。 然后从状态空间S'导出约束空间C'，其中C'是S'的逻辑补码。 对于多个选定的目标重复该过程，并且来自每个迭代的约束空间被逻辑地进行AND。 创建过近似抽象可能包括用随机门替换顺序门。 识别顺序门可以包括选择网表中的目标，执行目标的近似不正确的验证，并且如果发生虚假故障，则选择进一步向下沿当前选择的门的扇形链的门。
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公开(公告)号：US07322017B2
公开(公告)日：2008-01-22
申请号：US11011245
申请日：2004-12-14
CPC分类号： G06F17/504
摘要： A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is expanded to create a superset of the first initial state containing one or more states reachable from the first initial state of the design. A superset is synthesized to define a second initial state of the design. Application of the superset to the design is overapproximated through cutpoint insertion into the superset to obtain a modified superset, and the property is verified with reference to the modified superset.
摘要翻译： 公开了一种用于验证设计符合期望属性的方法，系统和计算机程序产品。 该方法包括接收设计，设计的第一初始状态和关于设计的验证的属性。 设计的第一初始状态被扩展以创建包含从设计的第一初始状态可访问的一个或多个状态的第一初始状态的超集。 合成超集以定义设计的第二初始状态。 超设计对设计的应用通过将切入点插入到超集中来获得修改后的超集，并且参考修改后的超集来验证该属性。
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公开(公告)号：US20060206842A1
公开(公告)日：2006-09-14
申请号：US11077331
申请日：2005-03-10
申请人： Jason Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
发明人： Jason Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method, system and computer program product for performing retiming in the presence of constraints are disclosed. The method comprises receiving an initial design containing one or more targets and one or more constraints and enumerating the one or more constraints and the one or more targets into a retiming gate set. A retiming graph is constructed from the initial design, and a retiming solution is obtained on the retiming graph. The retiming solution is normalized. One or more retiming lags from the retiming graph are propagated to the initial design, and the initial design is verified by using a constraint-satisfying analysis to determine whether the one or more targets may be hit while the one or more constraints are satisfied.
摘要翻译： 公开了一种用于在存在约束的情况下执行重新定时的方法，系统和计算机程序产品。 该方法包括接收包含一个或多个目标和一个或多个约束的初始设计，并将一个或多个约束和一个或多个目标列举到重定时门组中。 从初始设计构建重新定时图，并在重新定时图上获得重新定时解决方案。 重新定时解决方案被归一化。 来自重新定时图的一个或多个重新定时延迟被传播到初始设计，并且通过使用约束满足分析来确认初始设计，以确定在满足一个或多个约束的情况下是否可以命中一个或多个目标。
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6.发明授权Method and system for sequential netlist reduction through trace-containment 有权通过跟踪容纳进行顺序网表缩减的方法和系统公开(公告)号：US08015523B2
公开(公告)日：2011-09-06
申请号：US12392278
申请日：2009-02-25
CPC分类号： G06F17/505 , G06F17/504
摘要： Methods and systems are provided for sequential netlist reduction through trace-containment for a circuitry design netlist by first identifying a cut of the netlist and enumerating a set of mismatch traces. Perform time-bounded unfolding of a cofactored version of the cut to reflect the sequential cofactor for a specific input i and temporal uncorrelation constraints for the set of inputs ‘J’. Determine whether there is trace containment by performing equivalence checking with respect to the cut of the netlist under temporal uncorrelation constraints for the set of inputs ‘J’. In response to detecting trace containment, simplify the netlist by merging the input ‘i’ to a constant.
摘要翻译： 提供方法和系统，用于通过电路设计网表的跟踪容纳来顺序的网表减少，首先识别网表的剪切并列举一组不匹配的跟踪。 执行切片的辅助版本的时间限制展开，以反映特定输入i的顺序辅因子和输入集合J'的时间非相关约束。 通过对输入集合J'的时间不相关约束执行相对于网表的切分的等价性检查来确定是否存在跟踪容纳。 响应检测跟踪容纳，通过将输入'i'合并为常数来简化网表。
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7.发明申请Trace Containment Detection of Combinational Designs via Constraint-Based Uncorrelated Equivalence Checking 有权通过基于约束的不相关等价检查的组合设计的跟踪遏制检测公开(公告)号：US20100269077A1
公开(公告)日：2010-10-21
申请号：US12425095
申请日：2009-04-16
IPC分类号： G06F9/45
CPC分类号： G06F17/504
摘要： Methods and systems are provided for producing more efficient digital circuitry designs by identifying trace-containment for a sequential circuitry design netlist through the use of constraint-based uncorrelated equivalence checking. A set of candidate input netlist sets n1 and n2 is first uncorrelated and then submitted for equivalence checking. Mismatches discovered during the equivalence checking are avoided by imposing constraint to the input set until discovering an equivalency relationship between the input sets n1 and n2.
摘要翻译： 提供了方法和系统，用于通过使用基于约束的不相关等价检查来识别顺序电路设计网表的跟踪容纳来产生更有效的数字电路设计。 一组候选输入网表集n1和n2首先不相关，然后提交用于等价检查。 在等效检查期间发现的不匹配通过对输入集施加约束来避免，直到发现输入集n1和n2之间的等价关系。
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8.发明授权Method and system for performing target enlargement in the presence of constraints 失效在存在约束的情况下执行目标放大的方法和系统公开(公告)号：US07552407B2
公开(公告)日：2009-06-23
申请号：US12036093
申请日：2008-02-22
CPC分类号： G06F17/504
摘要： A method for performing verification is disclosed. The method includes receiving a design, including one or one or more targets, one or more constraints, one or more registers and one or more inputs. A first function of one of the one or more targets over the one or more registers and the one or more inputs is computed. A second function of one or more of the one or more constraints over the one or more registers and the one or more inputs is computed. The inputs of the first function and the second function are existentially quantified. A bounded analysis is performed to determine if the one of the one or more targets may be hit while adhering to the constraints. A preimage of the inputs of the first function and a preimage of the inputs of the second function is existentially quantified to create a synthesizable preimage. The synthesizable preimage is simplified and synthesized to create an enlarged target. Verification of the enlarged target is performed.
摘要翻译： 公开了一种用于执行验证的方法。 该方法包括接收包括一个或多个目标，一个或多个约束，一个或多个寄存器和一个或多个输入的设计。 计算一个或多个寄存器中的一个或多个目标之一和一个或多个输入的第一函数。 计算一个或多个寄存器和一个或多个输入中的一个或多个约束中的一个或多个的第二函数。 第一功能和第二功能的输入被存在量化。 执行有界分析以确定一个或多个目标中的一个是否可以在遵守约束的情况下被击中。 存在量化第一函数的输入和第二函数的输入的前像的前像，以创建可合成的前像。 可合成的前像被简化和合成，以创建一个扩大的目标。 执行放大目标的验证。
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公开(公告)号：US20080201128A1
公开(公告)日：2008-08-21
申请号：US11675698
申请日：2007-02-16
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022
摘要： A method and system for performing ternary verification is disclosed. Initially, a ternary model is generated from a binary model of a logic circuit design. The pairings used to encode the ternary model are then recorded. Next, the number of the recorded gate pairings is reduced by removing all invalid gate pairings. A ternary verification is performed on the ternary model having a reduced number of gate pairings.
摘要翻译： 公开了一种用于执行三元验证的方法和系统。 最初，从逻辑电路设计的二进制模型生成三元模型。 然后记录用于对三元模型进行编码的配对。 接下来，通过去除所有无效的门对配对来减少所记录的门对配对数。 对具有减少数量的门对配对的三元模型进行三进制验证。
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10.发明申请System and Method for Generating Constraint Preserving Testcases in the Presence of Dead-End Constraints 有权在死端约束存在下生成约束保存测试箱的系统和方法公开(公告)号：US20080195992A1
公开(公告)日：2008-08-14
申请号：US11673298
申请日：2007-02-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A system and method for generating constraint preserving testcases in the presence of dead-end constraints are provided. A balance between precision and computational expense in generating the testcases is achieved by establishing a sliding window of constraint solving for a selected number of K time-steps in the future from a current time-step. The testcases solve for the constraints for the next K time-steps at every state of a netlist instead of just trying to solve the constraint for the present time-step. K is determined by determining, for each input, either a minimum length path depth or maximum length depth path from the input to the constraint. The largest depth value for the inputs to the netlist is then utilized as the depth for the netlist. This depth then is used to define the width of the sliding window of constraint solving.
摘要翻译： 提供了一种用于在存在死区约束的情况下生成约束保留测试用例的系统和方法。 在生成测试用例时，精度和计算费用之间的平衡是通过从当前时间步骤中为将来选定数量的K个时间步骤建立一个约束求解滑动窗口来实现的。 测试用例解决了网表的每个状态下的下一个K时间步长的约束，而不是仅仅尝试解决当前时间步长的约束。 通过为每个输入确定从输入到约束的最小长度路径深度或最大长度深度路径来确定K。 网表的输入的最大深度值随后被用作网表的深度。 此深度用于定义约束求解的滑动窗口的宽度。
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