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公开(公告)号：US08566764B2
公开(公告)日：2013-10-22
申请号：US12771404
申请日：2010-04-30
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A mechanism is provided for increasing the scalability of transformation-based formal verification solutions through enabling the use of phase abstraction on logic models that include memory arrays. The mechanism manipulates the array to create a plurality of copies of its read and write ports, representing the different modulo time frames. The mechanism converts all write-before-read arrays to read-before-write and adds a bypass path around the array from write ports to read ports to capture any necessary concurrent read and write forwarding. The mechanism uses an additional set of bypass paths to ensure that the proper write data that becomes effectively concurrent through the unfolding inherent in phase abstraction is forwarded to the proper read port. If a given read port is disabled or fetches out-of-bounds data, the mechanism applies randomized data to the read port data output.
摘要翻译： 提供了一种机制，用于通过在包括存储器阵列的逻辑模型上使用相位抽象来增加基于变换的形式验证解决方案的可扩展性。 该机制操纵阵列以创建其读取和写入端口的多个副本，表示不同的模数时间帧。 该机制将所有写入前读数组转换为预写入，并将数组周围的旁路路径从写入端口读入端口，以捕获任何必需的并行读写转发。 该机制使用一组额外的旁路路径来确保通过展开固有的相位抽象将有效并发的正确写入数据转发到正确的读取端口。 如果给定的读取端口被禁用或获取超出范围的数据，则该机制将随机数据应用于读取端口数据输出。
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公开(公告)号：US20110271243A1
公开(公告)日：2011-11-03
申请号：US12771404
申请日：2010-04-30
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A mechanism is provided for increasing the scalability of transformation-based formal verification solutions through enabling the use of phase abstraction on logic models that include memory arrays. The mechanism manipulates the array to create a plurality of copies of its read and write ports, representing the different modulo time frames. The mechanism converts all write-before-read arrays to read-before-write and adds a bypass path around the array from write ports to read ports to capture any necessary concurrent read and write forwarding. The mechanism uses an additional set of bypass paths to ensure that the proper write data that becomes effectively concurrent through the unfolding inherent in phase abstraction is forwarded to the proper read port. If a given read port is disabled or fetches out-of-bounds data, the mechanism applies randomized data to the read port data output.
摘要翻译： 提供了一种机制，用于通过在包括存储器阵列的逻辑模型上使用相位抽象来增加基于变换的形式验证解决方案的可扩展性。 该机制操纵阵列以创建其读取和写入端口的多个副本，表示不同的模数时间帧。 该机制将所有写入前读数组转换为预写入，并将数组周围的旁路路径从写入端口读入端口，以捕获任何必需的并行读写转发。 该机制使用一组额外的旁路路径来确保通过展开固有的相位抽象将有效并发的正确写入数据转发到正确的读取端口。 如果给定的读取端口被禁用或获取超出范围的数据，则该机制将随机数据应用于读取端口数据输出。
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3.发明授权公开(公告)号：US08589837B1
公开(公告)日：2013-11-19
申请号：US13455839
申请日：2012-04-25
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/504
摘要： A computer-implemented method simplifies a netlist, verifies the simplified netlist using induction, and remaps resulting inductive counterexamples via inductive trace lifting within a multi-algorithm verification framework. The method includes: a processor deriving a first unreachable state information that can be utilized to simplify the netlist; performing a simplification of the netlist utilizing the first unreachable state information; determining whether the first unreachable state information can be inductively proved on an original version of the netlist; and in response to the first unreachable state information not being inductively provable on the original netlist: projecting the first unreachable state information to a minimal subset; and adding the projected unreachable state information as an invariant to further constrain a child induction process. Adding the projected state information as an invariant ensures that any resulting induction counterexamples can be mapped to valid induction counterexamples on the original netlist before undergoing the simplification.
摘要翻译： 计算机实现的方法简化网表，使用归纳验证简化的网表，并通过多算法验证框架内的归纳跟踪提升重新生成归纳反例。 该方法包括：处理器导出可用于简化网表的第一不可达状态信息; 利用第一不可达状态信息来执行网表的简化; 确定在网表的原始版本上是否可以感应地证明第一不可达状态信息; 并且响应于在原始网表上不被感应地证明的第一不可达状态信息：将第一不可达状态信息投射到最小子集; 并且将预测的不可达状态信息添加为不变量以进一步约束儿童归纳过程。 将投影状态信息添加为不变量确保在进行简化之前，任何导致的归因反例可以映射到原始网表上的有效归纳反例。
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4.发明授权Minimizing memory array representations for enhanced synthesis and verification 有权最小化存储器阵列表示，以增强综合和验证公开(公告)号：US08307313B2
公开(公告)日：2012-11-06
申请号：US12775607
申请日：2010-05-07
CPC分类号： G06F17/505
摘要： Mechanisms are provided in a design environment for minimizing memory array representations for enhanced synthesis and verification. The design environment comprises one mechanism to compress the width of arrays using disconnected pin information. The design environment comprises another mechanism to simplify the enable conditions of array ports using “don't care” computations. The design environment comprises yet another mechanism to reduce address pins from an array through analysis of limitations of readable addresses.
摘要翻译： 在用于最小化存储器阵列表示以用于增强的合成和验证的设计环境中提供机制。 设计环境包括使用断开的引脚信息压缩阵列宽度的一种机制。 设计环境包括使用无关心计算简化阵列端口使能条件的另一种机制。 设计环境包括通过分析可读地址的限制来减少地址引脚从阵列的另一机制。
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公开(公告)号：US20120054701A1
公开(公告)日：2012-03-01
申请号：US12871962
申请日：2010-08-31
CPC分类号： G06F17/504
摘要： Mechanisms are provided for refining an abstraction of a netlist for verification or synthesis of an integrated circuit design. The mechanisms receive an abstracted netlist corresponding to an original netlist of the integrated circuit design. The mechanisms determine elements already present in the abstracted netlist and refine the abstracted netlist by expanding the abstracted netlist to include additional elements that are correlated with the elements already present in the abstracted netlist to thereby generate a refined abstracted netlist. In addition, the mechanisms utilize the refined abstracted netlist to perform at least one of verification or synthesis of the integrated circuit design.
摘要翻译： 提供了用于改进用于验证或综合集成电路设计的网表的抽象的机制。 这些机制接收到与集成电路设计的原始网表相对应的抽象网表。 这些机制确定已经存在于抽象网表中的元素，并通过扩展抽象网表来改进抽象网表，以包括与抽象网表中已经存在的元素相关联的附加元素，从而生成精简抽象网表。 另外，这些机制利用精简的抽象网表来执行集成电路设计的验证或合成中的至少一个。
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公开(公告)号：US08589327B2
公开(公告)日：2013-11-19
申请号：US13092262
申请日：2011-04-22
CPC分类号： G06F17/504 , G06F17/11 , G06F2217/06
摘要： A mechanism is provided for efficiently determining Boolean satisfiability (SAT) using lazy constraints. A determination is made as to whether a SAT problem is satisfied without constraints in a list of constraints. Responsive to the SAT problem being satisfied without constraints, a set of variable assignments that are determined in satisfying the SAT problem without constraints are fixed. For each constraint in the list of constraints, a determination is made as to whether the SAT problem with the constraint results in the set of variable assignments remaining constant. Responsive to the SAT problem with the constraint resulting in the set of variable assignments remaining constant, the constraint is added to a list of non-affecting constraints and a satisfied result is returned.
摘要翻译： 提供了一种使用延迟约束有效地确定布尔可满足性（SAT）的机制。 确定SAT问题是否满足约束列表中的约束。 响应于没有约束的满足SAT问题的SAT问题，在不受约束的情况下满足SAT问题确定的一组可变分配是固定的。 对于约束列表中的每个约束，确定具有约束的SAT问题是否导致可变分配集合保持不变。 响应于导致变量赋值集合保持不变的约束的SAT问题，约束被添加到不受影响的约束的列表，并且返回满意的结果。
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7.发明授权Method and system for scalable reduction in registers with SAT-based resubstitution 失效用于基于SAT重新配置的寄存器的可缩减方法和系统公开(公告)号：US08473882B2
公开(公告)日：2013-06-25
申请号：US13415924
申请日：2012-03-09
CPC分类号： G06F17/505
摘要： A method, system, and computer program product for reducing the size of a logic network design, prior to verification of the logic network design. The method includes eliminating registers to reduce the size of the logic network design; thereby, increasing the speed and functionality of the verification process, and decreasing the size of the logic network design. The system identifies one or more compatible resubstitutions of a selected register, wherein the compatible resubstitution expresses the selected register as one or more pre-existing registers of fixed initial state. The resubstitutions are refined utilizing design invariants. When one more resubstitutions are preformed, the system eliminates the selected registers to reduce the size of the logic network design. As a result of the resubstitution process, a logic network design of reduced size is generated.
摘要翻译： 在验证逻辑网络设计之前，用于减小逻辑网络设计大小的方法，系统和计算机程序产品。 该方法包括消除寄存器以减小逻辑网络设计的大小; 从而增加验证过程的速度和功能，并减小逻辑网络设计的大小。 系统识别所选择的寄存器的一个或多个兼容的重新配置，其中兼容重新配置将所选择的寄存器表示为一个或多个预先存在的固定初始状态的寄存器。 利用设计不变量来改进重组。 当再进行一次重新配置时，系统将删除所选择的寄存器以减小逻辑网络设计的大小。 作为重新配置处理的结果，生成尺寸减小的逻辑网络设计。
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8.发明授权Techniques for employing retiming and transient simplification on netlists that include memory arrays 失效对包含存储器阵列的网表进行重新定时和瞬态简化的技术公开(公告)号：US08418106B2
公开(公告)日：2013-04-09
申请号：US12872490
申请日：2010-08-31
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A technique for performing an analysis of a logic design (that includes a native memory array embodied in a netlist) includes detecting an initial transient behavior in the logic design as embodied in the netlist. The technique also includes determining a duration of the initial transient behavior and gathering reduction information on the logic design based on the initial transient behavior. The netlist is then modified based on the reduction information.
摘要翻译： 用于执行对逻辑设计（包括在网表中包含的本地存储器阵列）的分析的技术包括检测在网表中体现的逻辑设计中的初始瞬态行为。 该技术还包括基于初始瞬态行为来确定初始瞬态行为的持续时间并收集关于逻辑设计的减少信息。 然后基于减少信息来修改网表。
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9.发明申请LOGICAL CIRCUIT NETLIST REDUCTION AND MODEL SIMPLIFICATION USING SIMULATION RESULTS CONTAINING SYMBOLIC VALUES 失效使用包含符号值的模拟结果的逻辑电路网络列表减少和模型简化公开(公告)号：US20120290992A1
公开(公告)日：2012-11-15
申请号：US13104573
申请日：2011-05-10
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A logic synthesis program, method and system for simplifying and/or reducing a logic design receives output from a logic simulator that uses symbolic values for stimulus and contains symbolic values in the logic simulator output. Relationships between the nodes dependent on symbolic values can be used to merge nodes or otherwise simplify the logic design. Behaviors such as oscillators, transient values, identical signals, dependent logical states and chicken-switch determined states that depend on the symbolic values can be detected in the simulation results and the netlist simplified using the results of the detection. The netlist can be simplified by inserting registers to represent nodes that assume a symbolic value or combination based on symbolic values either statically or after an initial transient. Oscillating nodes can be replaced with equivalent oscillator circuits, and nodes having values dependent on chicken-switch operation can be detected and replaced with registers initialized from the chicken-switch input states.
摘要翻译： 用于简化和/或减少逻辑设计的逻辑综合程序，方法和系统从逻辑模拟器接收输出，该逻辑模拟器使用符号值作为刺激，并在逻辑模拟器输出中包含符号值。 依赖于符号值的节点之间的关系可用于合并节点或简化逻辑设计。 可以在仿真结果和使用检测结果简化的网表中检测到依赖于符号值的振荡器，瞬态值，相同信号，依赖逻辑状态和鸡开关确定状态等行为。 可以通过插入寄存器来简化网表，以代表以静态方式或初始瞬态之后基于符号值假设符号值或组合的节点。 振荡节点可以用等效的振荡器电路代替，并且可以检测具有取决于鸡开关操作的值的节点，并用从鸡开关输入状态初始化的寄存器替换振荡节点。
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10.发明授权Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays. 有权有效的冗余识别，冗余删除和在包括内存数组的设计中的顺序等价检查。公开(公告)号：US08146034B2
公开(公告)日：2012-03-27
申请号：US12771677
申请日：2010-04-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504
摘要： A mechanism is provided for efficient redundancy identification, redundancy removal, and sequential equivalence checking with designs including memory arrays. The mechanism includes an array merging component to optimally merge an array output such that if the address is out-of-bounds or the port is not asserted, the array output is converted to a random output. The mechanism also includes a component for determining the equivalence of enabled array outputs rather than the array outputs directly and creating an enabled array output. The mechanism also includes a component that precludes potentially-redundant array cells from participating in the sequential redundancy removal determination. This component first checks for compatibility of the corresponding arrays, then the corresponding read port enables and addresses, then the corresponding initial values, and finally checking that writes to the corresponding columns yield a compatible set of values.
摘要翻译： 提供了一种机制，用于有效的冗余识别，冗余删除和与包括存储器阵列的设计的顺序等同性检查。 该机制包括阵列合并组件，以最佳地合并阵列输出，以便如果地址超出边界或端口未被断言，阵列输出将转换为随机输出。 该机制还包括用于确定启用的阵列输出的等效性的组件，而不是直接对阵列输出进行创建并创建启用的阵列输出。 该机制还包括排除潜在冗余阵列单元参与顺序冗余移除确定的组件。 该组件首先检查相应阵列的兼容性，然后对应的读端口启用和地址，然后对应的初始值，最后检查对相应列的写入是否产生兼容的值集合。
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