公开(公告)号：US06760872B2

公开(公告)日：2004-07-06

申请号：US09812109

申请日：2001-03-19

申请人： Jay K. Gupta ,  Somnath Paul

发明人： Jay K. Gupta ,  Somnath Paul

IPC分类号： G01R3128

CPC分类号： G11C29/12

摘要： A circuit that may be used to support testing of a memory block. The circuit generally comprises a decoder and a generator. The decoder may be configured to (i) decode a command signal into an address field, an operation field, and a data field and (ii) present a control signal to the memory block in response to the operation field. The generator may be configured to (i) present an address signal to the memory block in response to the address field and (ii) present a data signal to the memory block in response to the data field.

摘要翻译： 可用于支持内存块测试的电路。 电路通常包括解码器和发生器。 解码器可以被配置为（i）将命令信号解码成地址字段，操作字段和数据字段，以及（ii）响应于操作字段向存储器块呈现控制信号。 发生器可以被配置为（i）响应于地址字段向存储器块呈现地址信号，并且（ii）响应于数据字段向存储器块呈现数据信号。

公开(公告)号：US07496109B1

公开(公告)日：2009-02-24

申请号：US10777286

申请日：2004-02-11

申请人： Jay K. Gupta ,  Somnath Paul

发明人： Jay K. Gupta ,  Somnath Paul

IPC分类号： H04L12/56

CPC分类号： H04L47/22 ,  H04L49/90

摘要： A packet processing system including an encapsulator engine, and a packet pre-processor coupled to the encapsulator engine. The packet pre-processor calculates a variation between an input data rate and a pre-determined output data rate. The input data rate is based on a number of data read requests. The packet pre-processor compensates for the variation by modifying the number of data read requests.

摘要翻译： 一种分组处理系统，包括封装引擎和耦合到封装引擎的分组预处理器。 分组预处理器计算输入数据速率和预定输出数据速率之间的变化。 输入数据速率基于多个数据读取请求。 分组预处理器通过修改数据读取请求的数量来补偿变化。

公开(公告)号：US06957309B1

公开(公告)日：2005-10-18

申请号：US10324308

申请日：2002-12-18

申请人： Jay K. Gupta ,  Somnath Paul

发明人： Jay K. Gupta ,  Somnath Paul

IPC分类号： G06F5/10 ,  G06F12/02

CPC分类号： G06F5/10 ,  G06F2205/062

摘要： In one embodiment, the invention is an apparatus. The apparatus includes a FIFO array having a first plurality of memory elements, each memory element having a predetermined number of bits, the FIFO array having a read pointer. The apparatus also includes a FIFO control register array having a second plurality of memory elements, each memory element of the second plurality corresponding to a memory element of the first plurality of memory elements, the read pointer suitable for accessing the FIFO control register array. The apparatus further includes a control logic block coupled to the FIFO control register array and the FIFO array. The control logic block is to receive a data value of the memory element of the FIFO control register array pointed to by the read pointer. The control logic block is also to signal the read pointer to stall responsive to the data value having a first value.

摘要翻译： 在一个实施例中，本发明是一种装置。 该装置包括具有第一多个存储元件的FIFO阵列，每个存储器元件具有预定数量的位，该FIFO阵列具有读指针。 该装置还包括具有第二多个存储元件的FIFO控制寄存器阵列，第二多个存储元件的每个存储元件对应于第一多个存储器元件的存储器元件，该读指针适于访问FIFO控制寄存器阵列。 该装置还包括耦合到FIFO控制寄存器阵列和FIFO阵列的控制逻辑块。 控制逻辑块用于接收由读指针指向的FIFO控制寄存器阵列的存储元件的数据值。 响应于具有第一值的数据值，控制逻辑块还将读取指针发信号通知停止。