公开(公告)号：US5917818A

公开(公告)日：1999-06-29

申请号：US761499

申请日：1996-12-06

申请人： Je Soo Ko ,  Sung Hyuk Choi ,  Ho Jae Lee ,  Jong Hyun Lee ,  Jae Guen Kim

发明人： Je Soo Ko ,  Sung Hyuk Choi ,  Ho Jae Lee ,  Jong Hyun Lee ,  Jae Guen Kim

IPC分类号： H04L12/26 ,  H04J3/16 ,  H04Q11/04 ,  H04J3/14

CPC分类号： H04Q11/0478 ,  H04J3/1611 ,  H04J2203/0005 ,  H04J2203/0057 ,  Y10S370/907

摘要： A synchronous digital hierarchy digital cross-connection apparatus. The apparatus includes a synchronous signal connecting unit having a STM-N signal receiving part, a reversely multiplexing part and a STM-N signal transmitting part; an AU frame phase arranging and signal supervising unit; and an AU switching unit. The AU frame phase arranging and signal supervising unit includes a downward signal inputting part, and AU frame aligner, a signal path supervisor, a downward signal outputting part, and upward signal inputting part, an unconnected signal supervising and generating part, a selector, an upward signal outputting part and a CPU interface.

摘要翻译： 一种同步数字分层数字交叉连接装置。 该装置包括具有STM-N信号接收部分，反向复用部分和STM-N信号发送部分的同步信号连接单元; 一个AU帧相位排列和信号监控单元; 和AU切换单元。 AU帧相位布置和信号监控单元包括下行信号输入部分和AU帧对准器，信号路径监控器，向下信号输出部分和向上信号输入部分，未连接的信号监控和生成部分，选择器， 向上信号输出部分和CPU接口。

公开(公告)号：US5914952A

公开(公告)日：1999-06-22

申请号：US758257

申请日：1996-11-27

申请人： Doo Seop Eom ,  Sung Hyuk Choi ,  Sung Eun Jin ,  Je Soo Ko ,  Jong Hyun Lee

发明人： Doo Seop Eom ,  Sung Hyuk Choi ,  Sung Eun Jin ,  Je Soo Ko ,  Jong Hyun Lee

IPC分类号： H04L12/933 ,  H04Q11/04 ,  H04L12/50

CPC分类号： H04L49/101 ,  H04J2203/0007

摘要： A cross-connection apparatus for tributary unit-12 signal included in a synchronous transfer module-N signal used as a connection signal between synchronous digital hierarchy network nodes, is provided, including, an input/output and tributary unit time switching means for receiving a signal structured in the form of a frame (HEBUS) made up with an administration unit 3 signal, identifier byte and bit interleaved parity byte, performing an administration unit 3 pointer processing, virtual container 3 path overhead processing and tributary unit-12 pointer processing in order to be connected to the switching network, and thus performing a tributary unit-12 unit switching function; and a space switching means for receiving a frame (LBUS) made up with the tributary unit-12 signal, identifier byte and bit interleaved parity byte, namely, an LBUS signal, from the input/output and tributary unit time switching means, the means performing and outputting a space switching operation with the signal.

摘要翻译： 提供了包括在用作同步数字分层网络节点之间的连接信号的同步传输模块-N信号中的支流单元12信号的交叉连接装置，包括：输入/输出和支路单元时间切换装置， 由管理单元3信号，标识符字节和比特交织奇偶校验字节构成的帧（HEBUS）形式的信号，执行管理单元3指针处理，虚拟容器3路径开销处理和支持单元12指针处理 顺序连接到交换网络，从而执行支路单元12单元切换功能; 以及空间切换装置，用于从输入/输出和支路单元时间切换装置接收由辅助单元12信号，标识符字节和比特交织的奇偶校验字节（即LBUS信号）构成的帧（LBUS），该装置 执行并输出具有该信号的空间切换操作。

公开(公告)号：US5696788A

公开(公告)日：1997-12-09

申请号：US758004

申请日：1996-11-27

申请人： Sung Hyuk Choi ,  Sung Eun Jin ,  Doo Seop Eom ,  Je Soo Ko ,  Jong Hyun Lee

发明人： Sung Hyuk Choi ,  Sung Eun Jin ,  Doo Seop Eom ,  Je Soo Ko ,  Jong Hyun Lee

IPC分类号： H04L12/26 ,  G06F11/277 ,  H04Q11/04 ,  G06F11/60

CPC分类号： G06F11/277 ,  H04J3/14 ,  H04J2203/006

摘要： The present invention relates to a circuit for searching a fault location in a device having a number of ASIC's, including a first BIP(Bit Interleaved Parity) generating unit, which is coupled to the input stage of the ASIC where a fault will be detected, for calculating and outputting BIP for the specific byte, which is one of overhead bytes that were already utilized, i.e., not in use in transmission line, during a certain period; a BIP extraction unit, which is in parallel connected with the first BIP generating unit, for extracting the same byte as said specific byte from overhead bytes, which are generated and inserted in the previous-stage ASIC, in order to compare with BIP inputted into the first BIP generating unit during a certain period; a BIP comparison unit for simply comparing the result outputted from the first BIP generating unit with the result outputted from the BIP extraction unit; a BIP accumulation unit for accumulating the results outputted by the BIP comparison unit; a BIP threshold interrupt processing unit for comparing the results accumulated by the BIP accumulation unit with the threshold value which is used as the reference for generating an interrrupt, and then externally outputting the compared result; a second BIP generating unit, which is coupled to the output stage of the ASIC, for calculating and then outputting BIP for all the bytes within the transmission line(HBUS) during a certain period in order to inspect the signal of HBUS to the next-stage ASIC; and a BIP inserting unit for inserting the result generated from the second BIP generating unit into the specific byte location whithin said transmission line.

摘要翻译： 本发明涉及一种用于搜索具有多个ASIC的设备中的故障位置的电路​​，该电路包括第一BIP（位交错奇偶校验）产生单元，该第一BIP（位交错奇偶校验）产生单元耦合到将检测故障的ASIC的输入级， 用于计算和输出特定字节的BIP，该特定字节是在一段时间内已经使用的开销字节之一，即在传输线中不使用的; BIP提取单元，其与第一BIP生成单元并联连接，用于从生成并插入前一级ASIC的开销字节中提取与所述特定字节相同的字节，以便与输入到 在一段时间内第一个BIP生成单元; BIP比较单元，用于简单地将从第一BIP产生单元输出的结果与从BIP提取单元输出的结果进行比较; BIP累加单元，用于累加由BIP比较单元输出的结果; BIP阈值中断处理单元，用于将由BIP累积单元累积的结果与用作产生中断的基准的阈值进行比较，然后从外部输出比较结果; 第二BIP生成单元，其耦合到ASIC的输出级，用于计算然后在一定时间段期间输出传输线（HBUS）内的所有字节的BIP，以便检查HBUS到下一代的信号。 阶段ASIC; 以及BIP插入单元，用于将从第二BIP生成单元生成的结果插入到所述传输线中的特定字节位置。

公开(公告)号：US07245641B2

公开(公告)日：2007-07-17

申请号：US10247174

申请日：2002-09-19

申请人： Chan Kim ,  Kyeong Soo Han ,  Je Soo Ko ,  Tae Whan Yoo ,  Jong Hyun Lee

发明人： Chan Kim ,  Kyeong Soo Han ,  Je Soo Ko ,  Tae Whan Yoo ,  Jong Hyun Lee

IPC分类号： H04J3/04 ,  H04J3/02 ,  H04L12/50 ,  H04Q11/00

CPC分类号： H04L49/606 ,  H04L49/25 ,  H04L49/30 ,  H04L49/40 ,  H04L49/608 ,  H04L2012/562 ,  H04L2012/5651

摘要： Disclosed herein is a variable length packet switching system. The variable length packet switching system includes at least two switching means, a plurality of multiplexing units and a plurality of demultiplexing units. The switching means switch ATM cells or variable length packet data in parallel. The multiplexing means are arranged upstream of the switching means for multiplexing data inputted from a line card to the switching means in packet units and dividing a packet into packets of a number corresponding to the number of the switching means. The demultiplexing means are arranged downstream of the switching means for combining packets inputted after being switched in parallel by the at least two switching means and outputting the combined packet converted into a format adequate to the line card.

摘要翻译： 这里公开了一种可变长度分组交换系统。 可变长度分组交换系统包括至少两个切换装置，多个复用单元和多个解复用单元。 切换装置并行切换ATM信元或可变长度分组数据。 复用装置设置在切换装置的上游，用于将从线卡输入的数据以分组单元复用到切换装置，并将分组划分成与切换装置的数量相对应的数目的分组。 解复用装置设置在切换装置的下游，用于组合由至少两个切换装置并行切换之后输入的分组，并输出转换成适合于线卡的格式的组合分组。

公开(公告)号：US07624311B2

公开(公告)日：2009-11-24

申请号：US11947349

申请日：2007-11-29

申请人： Jong Yoon Shin ,  Hyun Jae Lee ,  Je Soo Ko

发明人： Jong Yoon Shin ,  Hyun Jae Lee ,  Je Soo Ko

IPC分类号： G06K5/04

CPC分类号： H04J3/1611 ,  H04L25/14

摘要： Provided are a method and an apparatus for converting an interface between high speed data having various capacities. The apparatus includes a data transmitting part and a data receiving part. The data transmitting part generates a deskew channel having respective timing data of a plurality of data transmitted from a first communicating device, and outputs the generated deskew channel together with the plurality of data to a second communicating device. The data receiving part compares the deskew channel transmitted from the second communicating device with the plurality of data to measure skew values of the data, aligns bits and bytes of the plurality of data using the skew values, and transmits the plurality of data to the first communicating device.

摘要翻译： 提供了一种用于转换具有各种容量的高速数据之间的接口的方法和装置。 该装置包括数据发送部分和数据接收部分。 数据发送部生成具有从第一通信装置发送的多个数据的各自的定时数据的歪斜通道，并将生成的歪斜通道与多个数据一起输出到第二通信装置。 数据接收部将从第二通信装置发送的歪斜通道与多个数据进行比较，以测量数据的偏斜值，使用偏斜值对准多个数据的比特和字节，并将多个数据发送到第一个 通讯设备

公开(公告)号：US20090150708A1

公开(公告)日：2009-06-11

申请号：US12316280

申请日：2008-12-11

申请人： Jongho Kim ,  Jong Yoon Shin ,  Je Soo Ko

发明人： Jongho Kim ,  Jong Yoon Shin ,  Je Soo Ko

IPC分类号： G06F11/00 ,  H04L29/04

CPC分类号： H04L25/14 ,  H03M9/00

摘要： The development of transmission technologies have resulted in a several tens Gbps optical transmission system. In the present invention, a low-speed FPGA receives a plurality of several Gbps signals according to a very high-speed parallel converting unit and the SFI-5, divides each of the plurality of several Gbps signals into a plurality of several hundreds (Mbps) parallel signals, and processes the plurality of several hundreds (Mbps) parallel signals in order to constitute an SFI-5 receiving end.

摘要翻译： 传输技术的发展已经导致了数十Gbps光传输系统。 在本发明中，低速FPGA根据非常高速的并行转换单元接收多个Gbps信号，并且SFI-5将多个Gbps信号中的每一个分成多个数百（Mbps） ）并行信号，并且处理多个数百个（Mbps）并行信号，以构成SFI-5接收端。

公开(公告)号：US20080313253A1

公开(公告)日：2008-12-18

申请号：US12051503

申请日：2008-03-19

申请人： Jong-Yoon Shin ,  Hanho Lee ,  Seungbeom Lee ,  Je Soo Ko

发明人： Jong-Yoon Shin ,  Hanho Lee ,  Seungbeom Lee ,  Je Soo Ko

IPC分类号： G06F11/08

CPC分类号： H03M13/1535 ,  H03M13/6575

摘要： Provided are an operation circuit for a modified Euclidean algorithm in a high-speed Reed-Solomon (RS) decoder and a method of implementing the modified Euclidean algorithm. Since a finite state machine (FSM) for generating a stop signal and an FSM for generating a control signal that controls a swap operation, a shift operation, and a polynomial operation for each basic cell of the modified Euclidean algorithm are used, an area-efficient RS decoder can be realized without using a conventional degree computation unit for comparing and calculating degrees.

摘要翻译： 提供了一种用于高速里德 - 所罗门（RS）解码器中的修改的欧几里德算法的操作电路和实现修改的欧几里德算法的方法。 由于使用用于产生停止信号的有限状态机（FSM）和用于产生控制交换操作的控制信号的FSM，所以使用修改的欧几里德算法的每个基本单元的移位操作和多项式操作， 可以在不使用用于比较和计算度的常规度计算单元的情况下实现高效的RS解码器。

公开(公告)号：US07412173B2

公开(公告)日：2008-08-12

申请号：US10802762

申请日：2004-03-18

申请人： Dong Soo Lee ,  Man Seop Lee ,  Sang Soo Lee ,  Je Soo Ko

发明人： Dong Soo Lee ,  Man Seop Lee ,  Sang Soo Lee ,  Je Soo Ko

IPC分类号： H04B10/04

CPC分类号： H04B10/505 ,  H04B10/5051 ,  H04B10/508

摘要： An apparatus for generating a Carrier-Suppressed Return-to-Zero (CS-RZ) signal is disclosed. The apparatus includes a mixer, a Low Pass Filter (LPF), a driver amplifier and a single external modulator. The mixer generates a modulator input by mixing data with a half clock signal. The LPF band-limits the modulator input data into low frequency band data. The driver amplifier amplifies the modulator input data generated by the mixing of the mixer and the band-limiting of the LPF. The external modulator generates CS-RZ signal, in which the phases of adjacent pulses have been inverted, by applying bias voltage to the modulator input data to be placed at the null point of the transfer function of the external modulator.

摘要翻译： 公开了一种用于产生载波抑制归零（CS-RZ）信号的装置。 该装置包括混频器，低通滤波器（LPF），驱动放大器和单个外部调制器。 混频器通过将数据与半个时钟信号混合来产生调制器输入。 LPF频带将调制器输入数据限制为低频带数据。 驱动器放大器放大由混频器混频产生的调制器输入数据和LPF的带限制。 外部调制器通过向调制器输入数据施加偏置电压而产生CS-RZ信号，其中相邻脉冲的相位已被反相，以将其置于外部调制器的传递函数的零点。

公开(公告)号：US07330664B2

公开(公告)日：2008-02-12

申请号：US10860903

申请日：2004-06-03

申请人： Wangjoo Lee ,  Hyunwoo Cho ,  Ki Ho Han ,  Je Soo Ko

发明人： Wangjoo Lee ,  Hyunwoo Cho ,  Ki Ho Han ,  Je Soo Ko

IPC分类号： H04B10/04 ,  H04B10/00

CPC分类号： H04B10/505 ,  H04B10/541

摘要： The present invention relates to none return to zero (NRZ) modulation method. The NRZ optical modulation is performed by combining a clock signal and NRZ data at a sending end and signal distortion capable of being generated when the clock signal and the NRZ data are combined is optimized by controlling the magnitude and phase of the clock signal. At the receiving end, the clock signal is extracted by performing narrow band band-pass filtering of the detected optical signal transmitted from a transmitter and data is recovered using the clock signal. Therefore, a receiver structure for clock extraction is simpler, an error rate of data recovery is lower by clearly extracting the clock signal, and transmission distance of the optical signal is longer.

公开(公告)号：US07796621B2

公开(公告)日：2010-09-14

申请号：US12184468

申请日：2008-08-01

申请人： Seung Hwan Kim ,  Je Soo Ko

发明人： Seung Hwan Kim ,  Je Soo Ko

IPC分类号： H04W4/00 ,  H04L12/28 ,  H04L12/56 ,  H04J3/04

CPC分类号： H04L12/413

摘要： Provided is an apparatus for matching Gigabit Ethernet (GbE) signals to an Optical Transport Hierarchy (OTH). The apparatus real-time records a source address and input port information of GbE Ethernet frames in a memory, compares a destination address of the Ethernet frame which is a payload of a GFP frame with memory table information, searches an output port location of the GbE, and interreceives GbE frames and Generic Frame Procedure (GFP) frames by multiplexing/demultiplexing.

摘要翻译： 提供了一种用于将千兆以太网（GbE）信号与光传送层级（OTH）相匹配的装置。 该装置实时记录存储器中的GbE以太网帧的源地址和输入端口信息，将作为GFP帧的有效载荷的以太网帧的目的地地址与存储器表信息进行比较，搜索GbE的输出端口位置 ，并通过复用/解复用来互连GbE帧和通用帧过程（GFP）帧。