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    DRAM access command queuing structure
    1.
    发明申请
    DRAM access command queuing structure 有权
    DRAM访问命令排队结构

    公开(公告)号：US20060026342A1

    公开(公告)日：2006-02-02

    申请号：US10899937

    申请日：2004-07-27

    申请人： Jean Calvignac ,  Chih-Jen Chang ,  Gordon Davis ,  Fabrice Verplanken

    发明人： Jean Calvignac ,  Chih-Jen Chang ,  Gordon Davis ,  Fabrice Verplanken

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1642

    摘要： Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.

    摘要翻译： 访问仲裁器被用于将对DRAM存储器件，特别是快速循环DRAM中的各个存储体的读取和写入访问请求进行优先级排序。 这用于通过避免对同一存储体的连续访问并且通过最小化死循环来优化用于读取和写入操作的存储器带宽。 仲裁器首先将DRAM访问划分为写访问和读访问。 访问请求被划分为每个存储体的访问，并且对每个存储体的访问次数施加了阈值限制。 基于写入队列状态，写入接收数据包在存储体之间旋转。 每个存储体的写入队列的状态也可以用于系统流控制。 仲裁器还通常包括基于命令队列的状态来确定访问窗口的能力，并且在每个访问窗口上执行仲裁。

    Split socket send queue apparatus and method with efficient queue flow control, retransmission and sack support mechanisms
    8.
    发明申请
    Split socket send queue apparatus and method with efficient queue flow control, retransmission and sack support mechanisms 失效

    公开(公告)号：US20060212563A1

    公开(公告)日：2006-09-21

    申请号：US11418606

    申请日：2006-05-05

    申请人： William Boyd ,  Jean Calvignac ,  Chih-Jen Chang ,  Douglas Joseph ,  Renato Recio

    发明人： William Boyd ,  Jean Calvignac ,  Chih-Jen Chang ,  Douglas Joseph ,  Renato Recio

    IPC分类号： G06F15/173

    CPC分类号： H04L47/10 ,  H04L47/193 ,  H04L69/12 ,  H04L69/16 ,  H04L69/161 ,  H04L69/162

    摘要： A mechanism for offloading the management of send queues in a split socket stack environment, including efficient split socket queue flow control and TCP/IP retransmission support. As consumers initiate send operations, send work queue entries (SWQEs) are created by an Upper Layer Protocol (ULP) and written to the send work queue (SWQ). The Internet Protocol Suite Offload Engine (IPSOE) is notified of a new entry to the SWQ and it subsequently reads this entry that contains pointers to the data that is to be transmitted. After the data is transmitted and acknowledgments are received, the IPSOE creates a completion queue entry (CQE) that is written into the completion queue (CQ). After the CQE is written, the ULP subsequently processes the entry and removes it from the CQE, freeing up a space in both the SWQ and CQ. The number of entries available in the SWQ are monitored by the ULP so that it does not overwrite any valid entries. Likewise, the IPSOE monitors the number of entries available in the CQ, so as not overwrite the CQ. The flow control between the ULP and the IPSOE is credit based. The passing of CQ credits is the only explicit mechanism required to manage flow control of both the SWQ and the CQ between the ULP and the IPSOE.

    Receive queue device with efficient queue flow control, segment placement and virtualization mechanisms
    9.
    发明申请
    Receive queue device with efficient queue flow control, segment placement and virtualization mechanisms 有权
    接收具有高效队列流控制，段放置和虚拟化机制的队列设备

    公开(公告)号：US20060259644A1

    公开(公告)日：2006-11-16

    申请号：US11487265

    申请日：2006-07-14

    申请人： William Boyd ,  Jean Calvignac ,  Chih-Jen Chang ,  Douglas Joseph ,  Renato Recio

    发明人： William Boyd ,  Jean Calvignac ,  Chih-Jen Chang ,  Douglas Joseph ,  Renato Recio

    IPC分类号： G06F15/16

    CPC分类号： H04L69/16 ,  H04L69/12 ,  H04L69/161

    摘要： A mechanism for offloading the management of receive queues in a split (e.g. split socket, split iSCSI, split DAFS) stack environment, including efficient queue flow control and TCP/IP retransmission support. An Upper Layer Protocol (ULP) creates receive work queues and completion queues that are utilized by an Internet Protocol Suite Offload Engine (IPSOE) and the ULP to transfer information and carry out send operations. As consumers initiate receive operations, receive work queue entries (RWQEs) are created by the ULP and written to the receive work queue (RWQ). The ISPOE is notified of a new entry to the RWQ and it subsequently reads this entry that contains pointers to the data that is to be received. After the data is received, the IPSOE creates a completion queue entry (CQE) that is written into the completion queue (CQ). After the CQE is written, the ULP subsequently processes the entry and removes it from the CQE, freeing up a space in both the RWQ and CQ. The number of entries available in the RWQ are monitored by the ULP so that it does not overwrite any valid entries. Likewise, the IPSOE monitors the number of entries available in the CQ, so as not overwrite the CQ.

    摘要翻译： 一种用于卸载分裂（例如，分裂式插座，拆分式iSCSI，拆分式DAFS）堆栈环境中接收队列管理的机制，包括有效的队列流控制和TCP / IP重传支持。 上层协议（ULP）创建互联网协议套件卸载引擎（IPSOE）和ULP利用的接收工作队列和完成队列，以传输信息并执行发送操作。 当消费者开始接收操作时，接收工作队列条目（RWQE）由ULP创建并写入接收工作队列（RWQ）。 通知ISPOE对RWQ的新条目，并随后读取包含要接收的数据的指针的该条目。 接收到数据后，IPSOE创建写入完成队列（CQ）的完成队列条目（CQE）。 在编写CQE之后，ULP随后处理该条目并将其从CQE中移除，释放了RWQ和CQ两者中的空间。 RWQ中可用的条目数由ULP监视，以便它不会覆盖任何有效的条目。 同样，IPSOE监视CQ中可用条目的数量，以免覆盖CQ。

    Techniques for Connecting an External Network Coprocessor to a Network Processor Packet Parser
    10.
    发明申请
    Techniques for Connecting an External Network Coprocessor to a Network Processor Packet Parser 有权
    将外部网络协处理器连接到网络处理器数据包解析器的技术

    公开(公告)号：US20130308653A1

    公开(公告)日：2013-11-21

    申请号：US13884664

    申请日：2011-12-19

    申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Damon Philippe ,  Natarajan Vaidhyanathan ,  Colin B. Verrilli ,  Fabrice Jean Verplanken

    发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Damon Philippe ,  Natarajan Vaidhyanathan ,  Colin B. Verrilli ,  Fabrice Jean Verplanken

    IPC分类号： H04L29/06

    CPC分类号： H04L29/0653 ,  G06F9/3877 ,  G06F9/544 ,  G06F13/385 ,  G06F15/163 ,  H04L69/22

    摘要： A network processor includes first communication protocol ports that each support ‘M’ minimum size packet data path traffic on ‘N’ lanes at ‘S’ Gigabits per second (Gbps) and traffic with different communication protocol units on ‘n’ additional lanes at ‘s’ Gbps. The first communication protocol ports support access to an external coprocessor using parsing logic located in each of the first communication protocol ports. The parsing logic, during a parsing period, is configured to send a request to the external coprocessor at reception of a ‘M’ size packet and to receive a response from the external coprocessor. The parsing logic sends a request maximum ‘m’ size byte word to the external coprocessor on one of the additional lanes and receives a response maximum ‘m’ size byte word from the external coprocessor on the one of the additional lanes while complying with the equation N×S/M=

    摘要翻译： 网络处理器包括第一通信协议端口，每个端口以“S”千兆位/秒（Gbps）在“N”通道上支持“M”个最小尺寸分组数据路径业务，并且在“n”个附加车道上以不同的通信协议单元的流量“ s Gbps 第一通信协议端口支持使用位于每个第一通信协议端口中的解析逻辑来访问外部协处理器。 解析逻辑在解析周期期间被配置为在接收到“M”大小的分组时向外部协处理器发送请求并且从外部协处理器接收响应。 解析逻辑在附加通道之一上向外部协处理器发送请求最大“m”字节字，并在附加通道之一上从外部协处理器接收响应最大“m”字节字，同时遵循等式 N×S / M =