Methods and systems for barrier reduction in parallel processing systems
    1.
    发明授权
    Methods and systems for barrier reduction in parallel processing systems 有权
    并行处理系统中屏障减少的方法和系统

    公开(公告)号:US08392900B1

    公开(公告)日:2013-03-05

    申请号:US11082321

    申请日:2005-03-17

    IPC分类号: G06F9/45

    CPC分类号: G06F8/458 G06F9/522

    摘要: Systems and methods according to the present invention provide techniques which modify programs having barrier statements. Dependence relations between statements, and enforcement associations between the barrier statements and the dependence relations, in the program are identified. The dependence relations are classified as being either enforceable by point-to-point synchronization or not enforceable by point-to-point synchronization. A subset of the barrier statements, which will enforce those dependence relations that are unenforceable by point-to-point synchronization, are determined. Other(s) of the barrier statements are replaced with a point-to-point synchronization routine.

    摘要翻译: 根据本发明的系统和方法提供了修改具有屏障语句的程序的技术。 确定了程序中声明之间的依赖关系以及屏障声明与依赖关系之间的执行关联。 依赖关系被分类为可以通过点对点同步执行,或者不能通过点对点同步来执行。 确定屏障语句的子集,其将强制通过点对点同步不可执行的那些依赖关系。 其他的屏障语句被替换为点对点同步程序。

    Head of queue cache for communication interfaces
    2.
    发明授权
    Head of queue cache for communication interfaces 有权
    通讯接口队列缓存头

    公开(公告)号:US07650471B2

    公开(公告)日:2010-01-19

    申请号:US11326919

    申请日:2006-01-06

    IPC分类号: G06F12/10

    摘要: A technique includes identifying an address of a head end of a queue and monitoring a coherent interconnect to identify a data transfer that is communicated by a producer, which targets the address. The technique includes storing the data of the data transfer in the queue and selectively storing at least a portion of the data in a head-of-queue cache memory based at least in part on whether the monitoring identifies the address. At least a portion of the data is selectively retrieved from the head-of-queue cache memory instead of from the queue for transmission to a consumer.

    摘要翻译: 一种技术包括识别队列的头端的地址并监视相干互连以识别由生产者传送的数据传输,该生产者以该地址为目标。 该技术包括将数据传输的数据存储在队列中并且至少部分地基于监视是否识别地址来选择性地将至少一部分数据存储在队列头部高速缓冲存储器中。 从队列高速缓冲存储器而不是从队列中选择性地检索至少一部分数据以传送给消费者。

    Message queue tuning
    3.
    发明申请
    Message queue tuning 审中-公开
    消息队列调优

    公开(公告)号:US20060059257A1

    公开(公告)日:2006-03-16

    申请号:US10940173

    申请日:2004-09-14

    IPC分类号: G06F15/173

    CPC分类号: G06F9/546 H04L49/90

    摘要: Message queue tuning is disclosed. A communication routine is provided that is able to record a log entry for a message. A log is obtained by running a software application with the communication routine. The log is evaluated to determine a desired value of a tuning knob for a message queue parameter of the communication routine, and the tuning knob is adjusted to the desired value for running the software application with the communication routine.

    摘要翻译: 消息队列调优被公开。 提供了能够记录消息的日志条目的通信例程。 通过运行具有通信例程的软件应用程序获得日志。 评估日志以确定通信例程的消息队列参数的调谐旋钮的期望值,并且通过通信例程将调谐旋钮调整到用于运行软件应用程序的期望值。

    Method and system for optional code scheduling
    4.
    发明申请
    Method and system for optional code scheduling 有权
    可选代码调度的方法和系统

    公开(公告)号:US20060026582A1

    公开(公告)日:2006-02-02

    申请号:US10902199

    申请日:2004-07-28

    IPC分类号: G06F9/45

    CPC分类号: G06F8/443

    摘要: A method of scheduling optional instructions in a compiler targets a processor. The scheduling includes indicating a limit on the additional processor computations that are available for executing an optional code, generating one or more required instructions corresponding to a source code and one or more optional instructions corresponding to the optional code used with the source code and scheduling all of the one or more required instructions with as many of the one or more optional instructions as possible without exceeding the indicated limit on the additional processor computations for executing the optional code.

    摘要翻译: 在编译器中调度可选指令的方法针对处理器。 调度包括指示可用于执行可选代码的附加处理器计算的限制,生成对应于源代码的一个或多个所需指令以及对应于与源代码一起使用的可选代码的一个或多个可选指令并且调度所有 所述一个或多个所需指令具有尽可能多的一个或多个可选指令,而不超过用于执行可选代码的附加处理器计算的指定限制。

    Methods and systems for modifying software applications to implement memory allocation
    5.
    发明申请
    Methods and systems for modifying software applications to implement memory allocation 审中-公开
    用于修改软件应用程序以实现内存分配的方法和系统

    公开(公告)号:US20080005726A1

    公开(公告)日:2008-01-03

    申请号:US11477840

    申请日:2006-06-29

    IPC分类号: G06F9/45

    CPC分类号: G06F8/52

    摘要: Techniques for modifying applications to implement memory allocation are disclosed. The application is executed using a default memory allocation scheme. A log is generated that identifies which memory addresses are requested by which instructions of the application. The log is evaluated to identify changes to be made to the default memory allocation scheme and, after execution, the application is modified by adding instructions to implement the identified changes.

    摘要翻译: 公开了用于修改应用以实现内存分配的技术。 应用程序使用默认内存分配方案执行。 生成一个日志,用于标识应用程序的哪个指令请求哪些内存地址。 评估日志以识别对默认内存分配方案的更改,并且在执行后,通过添加指令来修改应用程序来实现所标识的更改。

    Determination of loop unrolling factor for software loops
    6.
    发明申请
    Determination of loop unrolling factor for software loops 审中-公开
    确定软件循环的循环展开因子

    公开(公告)号:US20050283772A1

    公开(公告)日:2005-12-22

    申请号:US10874614

    申请日:2004-06-22

    IPC分类号: G06F9/45

    CPC分类号: G06F8/4452

    摘要: Disclosed are embodiments of a method and system for calculating an unrolling factor for software loops. The unrolling factor may be calculated by applying a formula that takes into account issue constraints of a processor. The issue constraints may include the total issue width of the processor, and may also include individual issue constraints for each instruction type. The software loop may be unrolled by the calculated unrolling factor and may be software pipelined. Other embodiments are also described and claimed.

    摘要翻译: 公开了用于计算软件循环的展开因子的方法和系统的实施例。 可以通过应用考虑到处理器的问题约束的公式来计算展开因子。 问题约束可以包括处理器的总发行宽度,并且还可以包括针对每个指令类型的单独的问题约束。 软件循环可以通过计算的展开因子展开,并且可以是软件流水线的。 还描述和要求保护其他实施例。

    Detecting memory address bounds violations
    7.
    发明申请
    Detecting memory address bounds violations 审中-公开
    检测内存地址限制违规

    公开(公告)号:US20050283770A1

    公开(公告)日:2005-12-22

    申请号:US10871971

    申请日:2004-06-18

    IPC分类号: G06F9/45

    CPC分类号: G06F11/366 G06F11/3624

    摘要: In one aspect, machine-executable code is generated. The machine-executable code includes machine-readable instructions for detecting a memory address bounds violation by the program code based on a determination that a boundary memory address stored in a hardware table has been accessed during execution of the program code. The boundary memory address delimits a boundary for a set of memory addresses allocated for execution of the program code. The machine-executable code is stored in a machine-readable medium. In another aspect, a boundary memory address delimiting a boundary for a set of memory addresses allocated for execution of the program code is stored in a hardware table. The program code is executed. A memory address bounds violation by the program code is detected based on a determination that the boundary memory address stored in the hardware table has been accessed during execution of the program code.

    摘要翻译: 在一个方面,生成机器可执行代码。 机器可执行代码包括用于基于在执行程序代码期间存储在硬件表中的边界存储器地址已经被访问的确定来检测存储器地址限制程序代码的机器可读指令。 边界存储器地址限定分配用于执行程序代码的一组存储器地址的边界。 机器可执行代码存储在机器可读介质中。 另一方面,分配用于执行程序代码的一组存储器地址的边界的边界存储器地址被存储在硬件表中。 执行程序代码。 基于在执行程序代码期间存储在硬件表中的边界存储器地址已经被访问的确定来检测存储器地址限制程序代码的违规。

    Prioritized polling for virtual network interfaces
    9.
    发明授权
    Prioritized polling for virtual network interfaces 有权
    虚拟网络接口的优先轮询

    公开(公告)号:US08364874B1

    公开(公告)日:2013-01-29

    申请号:US11332956

    申请日:2006-01-17

    IPC分类号: G06F13/00 G06F13/36

    CPC分类号: G06F9/5027 G06F2209/5021

    摘要: Methods and systems for prioritizing virtual network interface controllers (VNICs) are described. Each VNIC is assigned a priority level and a maximum current priority level associated with VNICs which are requesting service is determined. Fairness is enforced by using a round robin approach to selection among those currently requesting VNICs which have the same, maximum current priority level.

    摘要翻译: 描述了用于优先化虚拟网络接口控制器(VNIC)的方法和系统。 每个VNIC被分配优先级,并且确定与请求服务的VNIC相关联的最大当前优先级。 通过使用循环方法在当前请求具有相同的最大当前优先级的VNIC之间进行选择来实施公平。