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1.发明授权Method and apparatus for generating a control power delivered to a load by a polyphase power line 失效用于产生由多相电力线传送到负载的控制功率的方法和装置
公开(公告)号：US4670831A
公开(公告)日：1987-06-02
申请号：US756621
申请日：1985-07-19
CPC分类号： H02M7/1623 , H02P7/293
摘要： A microprocessor determines the zero cross-over times and direction of the phase voltages of the AC power line; a multiplexer has three parallel inputs which are respectively connected to the three phase conductors of the line and an output delivering a voltage formed by successive portions of the phase voltages; a flip-flop sensitive to the change of sign is connected to the output of the multiplexer; and EXCLUSIVE OR gate has an input connected to the output of the flip-flop and an other input to an output of the processor; and a NAND gate has an input connected to the output of the EXCLUSIVE OR gate and another input which receives a signal formed of a succession of square waves forming enabling windows.
摘要翻译： 微处理器确定交流电源线的相电压的零交叉时间和方向; 多路复用器具有分别连接到该线路的三相导线的三个并行输入端和一个输出由相电压的连续部分形成的电压的输出端; 对符号变化敏感的触发器连接到多路复用器的输出; 并且EXCLUSIVE或门具有连接到触发器的输出的输入端和与处理器的输出端的另一输入端; 并且NAND门具有连接到EXCLUSIVE OR门的输出的输入端和接收由形成启用窗口的一系列方波形成的信号的另一输入端。
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公开(公告)号：US4683545A
公开(公告)日：1987-07-28
申请号：US642326
申请日：1984-08-20
CPC分类号： G01P3/489
摘要： A process for determining a speed and a device for implementing same are provided, wherein the counting device comprises a microprocessor, a programmable counting circuit comprising three counters and connected to the address/data bus of the microprocessor, a storage flip-flop circuit storing the selection addresses of the counters, each counter being associated with a register for preselection of a value for reinitialization of the counters and a common register of the counted values. A logic circuit receiving a masking signal produced by the third counter transfers, to the INTO input of the microprocessor, interruption signals.
摘要翻译： 提供了一种用于确定速度的过程和用于实现速度的装置，其中计数装置包括微处理器，包括三个计数器并连接到微处理器的地址/数据总线的可编程计数电路，存储触发器电路 计数器的选择地址，每个计数器与用于预选择计数器重新初始化的值的寄存器和计数值的公共寄存器相关联。 接收由第三计数器产生的掩蔽信号的逻辑电路将中断信号传送到微处理器的INT＆upbar＆O输入。
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3.发明授权Process and device for determining the mean value of the current delivered by a controllable valve rectifier bridge 失效用于确定由可控阀整流桥传递的电流的平均值的过程和装置
公开(公告)号：US4638419A
公开(公告)日：1987-01-20
申请号：US756550
申请日：1985-07-19
CPC分类号： G01R19/003 , G01R19/22 , H02M7/1626
摘要： A process and device are provided for determining the mean value of the current delivered by a thyristor rectifier bridge fed by a multiphase AC network. Said device comprises successively an operational amplifier whose inverting input receives a signal representative of the current supplied by the bridge and is connected to its output by a capacitor, a blocking sampler and an analog-digital converter. The switch and the blocking sampler are controlled by a microprocessor so as to obtain an integration cycle and end of cycle sampling during a period zone of value (T/6), (T) being the period of the network.
摘要翻译： 提供了一种过程和装置，用于确定由多相AC网络馈送的可控硅整流桥传递的电流的平均值。 所述装置依次包括运算放大器，其反相输入端接收代表由桥提供的电流的信号，并通过电容器，阻塞采样器和模拟数字转换器连接到其输出端。 交换机和阻塞采样器由微处理器控制，以在值（T / 6），（T）作为网络周期的周期区域内获得积分周期和周期采样结束。
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