公开(公告)号：US20050267705A1

公开(公告)日：2005-12-01

申请号：US10709805

申请日：2004-05-28

申请人： Jeanne Bickford ,  Vernon Norman ,  Michael Ouellette ,  Mark Styduhar ,  Brian Worth

发明人： Jeanne Bickford ,  Vernon Norman ,  Michael Ouellette ,  Mark Styduhar ,  Brian Worth

IPC分类号： G01R31/28 ,  G06F19/00 ,  H01L21/66

CPC分类号： G01R31/2831 ,  H01L22/14

摘要： A method for providing quality control on wafers running on a manufacturing line is disclosed. The resistances on a group of manufacturing test structures within a wafer running on a wafer manufacturing line are initially measured. Then, an actual distribution value is obtained based on the result of the measured resistances on the group of manufacturing test structures. The difference between the actual distribution value and a predetermined distribution value is recorded. The predetermined distribution value is previously obtained based on a ground rule resistance. Next, the resistances on a group of design test structures within the wafer are measured. The measured resistances of the group of design test structures are correlated to the measured resistances of the group of manufacturing test structures in order to obtain an offset value. The resistance of an adjustable resistor circuit within the wafer is then adjusted accordingly, and subsequent wafers running on the wafer manufacturing line are also adjusted according to the offset value.

摘要翻译： 公开了一种用于对在生产线上运行的晶片进行质量控制的方法。 初始测量在晶片生产线上运行的晶片内的一组制造测试结构的电阻。 然后，基于制造试验结构体的测定电阻的结果，求出实际的分布值。 记录实际分布值与预定分布值之间的差。 基于接地规则电阻预先获得预定分布值。 接下来，测量晶片内的一组设计测试结构的电阻。 设计测试结构组的测量电阻与制造测试结构组的测量电阻相关，以获得偏移值。 然后相应地调节晶片内的可调节电阻电路的电阻，并且还根据偏移值来调整在晶片制造线上运行的后续晶片。

公开(公告)号：US20080086706A1

公开(公告)日：2008-04-10

申请号：US11941342

申请日：2007-11-16

申请人： Corey Barrows ,  Douglas Kemerer ,  Stephen Shuma ,  Douglas Stout ,  Oscar Strohacker ,  Mark Styduhar ,  Paul Zuchowski

发明人： Corey Barrows ,  Douglas Kemerer ,  Stephen Shuma ,  Douglas Stout ,  Oscar Strohacker ,  Mark Styduhar ,  Paul Zuchowski

IPC分类号： G06F17/50

CPC分类号： G06F17/5063 ,  H01L27/088 ,  H01L27/092

摘要： A design structure. The design structure includes: a first set of FETs having a designed first Vt and a second set of FETs having a designed second Vt, the first Vt different from the second Vt; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and of the second monitor circuit; a control unit responsive to the compare signal and configured to generate a control signal regulator based on the compare signal; and an adjustable voltage regulator responsive to the control signal and configured to voltage bias wells of FETs of the second set of FETs, the value of the voltage bias applied based on the control signal.

摘要翻译： 设计结构。 该设计结构包括：具有设计的第一V FET的第一组FET和具有设计的第二V FET的第二组FET，第一V T 与第二V 不同; 包含第一组FET的至少一个FET的第一监视器电路和包含第二组FET的至少一个FET的第二监视电路; 比较电路，被配置为基于所述第一监视电路和所述第二监视电路的性能测量来产生比较信号; 控制单元，响应于比较信号并被配置为基于比较信号产生控制信号调节器; 以及响应于所述控制信号并被配置为所述第二组FET的FET的电压偏置阱的可调电压调节器，所述电压偏置值基于所述控制信号施加。

公开(公告)号：US20070168759A1

公开(公告)日：2007-07-19

申请号：US11164646

申请日：2005-11-30

申请人： Kenneth Goodnow ,  Oscar Strohacker ,  Mark Styduhar ,  Peter Twombly ,  Andrew Wienick ,  Paul Zuchowski ,  Stephen Shuma

发明人： Kenneth Goodnow ,  Oscar Strohacker ,  Mark Styduhar ,  Peter Twombly ,  Andrew Wienick ,  Paul Zuchowski ,  Stephen Shuma

IPC分类号： G06F11/00

CPC分类号： G06F11/008

摘要： Disclosed are embodiments of a method and an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system includes duplicate devices incorporated into the second system (e.g., on a shared bus). These duplicate devices are adapted to independently perform the same function within that second system. Reference signal generators, a reference signal comparator, a power controller and a state machine, working in combination, can be adapted to seamlessly switch performance of that same function within the second system between the duplicate devices based on a measurement of performance degradation to allow for device recovery. A predetermined policy accessible by the state machine dictates when and whether or not to initiate a switch.

摘要翻译： 公开了一种方法和相关联的第一系统的实施例，用于在存在导致在系统设备内展现性能下降和恢复性能的现象的情况下延长第二系统的产品寿命。 第一系统包括并入第二系统中的重复设备（例如，在共享总线上）。 这些重复设备适于在该第二系统内独立地执行相同的功能。 参考信号发生器，参考信号比较器，功率控制器和状态机组合起来可以适应于基于性能下降的测量来在复制设备之间的第二系统内的相同功能的无缝切换性能，以允许 设备恢复。 状态机可访问的预定策略指示何时以及是否启动切换。

公开(公告)号：US20050076170A1

公开(公告)日：2005-04-07

申请号：US10680756

申请日：2003-10-07

申请人： Michael Boudreaux ,  Adam Courchesne ,  Jason Norman ,  Mark Styduhar ,  Sebastian Ventrone

发明人： Michael Boudreaux ,  Adam Courchesne ,  Jason Norman ,  Mark Styduhar ,  Sebastian Ventrone

IPC分类号： G06F12/00

CPC分类号： G06F13/4269

摘要： A structure and associated method to control a flow of data on a semiconductor device. A transmitter, receiver and transmission line are formed within the semiconductor device. The transmitter, receiver, and transmission line are adapted to control data transfer between a first core and a second core within the semiconductor device. The transmitter is adapted to send a signal over the transmission line to the receiver adapted to receive the signal. The receiver is further adapted to create an impedance mismatch to indicate that the second core is unable to transfer the data. The transmitter is adapted to detect the impedance mismatch.

摘要翻译： 一种用于控制半导体器件上的数据流的结构和相关方法。 在半导体器件内形成发射器，接收器和传输线。 发射器，接收器和传输线适于控制半导体器件内的第一芯和第二芯之间的数据传输。 发射机适于通过传输线路将信号发送到适于接收信号的接收机。 接收机还适于产生阻抗失配以指示第二核心不能传送数据。 发射机适用于检测阻抗失配。