摘要:
A method and apparatus for performing concurrent operations on the host bus, expansion bus, and local I/O bus as well as the processor bus connecting the processor and cache system to increase computer system efficiency. A plurality of CPU boards are coupled to a host bus which in turn is coupled to an expansion bus through a bus controller. Each CPU board includes a processor connected to a cache system including a cache controller and cache memory. The cache system interfaces to the host bus through address and data buffers controlled by cache interface logic. Distributed system peripheral (DSP) logic comprising various ports, timers, and interrupt controller logic is coupled to the cache system, data buffers, and cache interface logic by a local I/O bus. The computer system supports various areas of concurrent operation, including concurrent local I/O cycles, host bus snoop cycles and CPU requests, as well as concurrent expansion bus reads with snooped host bus cycles.
摘要:
A method and apparatus which reduces the non-snoop window of a cache controller during certain operations to increase host bus efficiency. The cache controller requires a bus grant signal to perform cycles and cannot snoop cycles after the bus grant signal has been provided until the cycle completes. Cache interface logic monitors the cache controller for cycles that require either the expansion bus or the local I/O bus. When such a cycle is detected, the apparatus begins the cycle and does not assert the bus grant signal to the cache controller. The cache controller thus believes that the cycle has not yet begun and is thus able to perform other operations, such as snooping other host bus cycles. During this time, the cycle executes. When the read data is returned or when the write data reaches its destination, the interface logic provides the bus grant cycle to the cache controller at an appropriate time. By delaying the bus grant signal in this manner, the non-snoop window is reduced.
摘要:
A method and apparatus for operating tightly coupled mirrored processors in a computer system. A plurality of CPU boards are coupled to a processor/memory bus, commonly called a host bus. Each CPU board includes a processor as well as various ports, timers, and interrupt controller logic local to the respective processor. The processors on one or more CPU boards are designated as master processors, with the processors on the remaining CPU boards being designated as mirroring or slave processors. A master processor has full access to the host bus and a second, multiplexed bus for read and write cycles, whereas the slave processors are prevented from writing to any bus. The slave processors compare write data and various control signals with that generated by its respective master processor for disparities. The system includes interrupt controller synchronization logic to synchronize interrupt requests as well as timer synchronization logic to synchronize the timers in each of the master and slave CPUs to guarantee that the master and slave CPUs operate in lockstep.
摘要:
Techniques are disclosed relating to a three-dimensional computer interface. In one embodiment, an apparatus is disclosed that includes a camera and a proximity sensor. The camera is configured to capture an image that includes an object. In some embodiments, the proximity sensor is configured to perform a measurement operation that includes determining only a single distance value for the object. The apparatus is configured to calculate a location of the object based on the captured image and the single distance value. In some embodiments, the apparatus is configured to determine a motion of the object by calculating a plurality of locations of the object. In some embodiments, the apparatus is configured to identify the object as a user's hand, and to control a depiction of content on a display based on the determined path of motion for the user's hand.
摘要:
A computer system which utilizes processor boards including a first level cache system integrated with the microprocessor, a second level external cache system and a third level external cache system. The second level cache system is a conventional, high speed, SRAM-based, writeback cache system. The third level cache system is a large, writethrough cache system developed using conventional DRAMs as used in the main memory subsystem of the computer system. The three cache systems are arranged between the CPU and the host bus in a serial fashion. Because of the large size of the third level cache, a high hit rate is developed so that operations are not executed on the host bus but are completed locally on the processor board, reducing the use of the host bus by an individual processor board. This allows additional processor boards to be installed in the computer system without saturating the host bus. The third level cache system is organized as a writethrough cache. However, the shared or exclusive status of any cached data is also stored. If the second level cache performs a write allocate cycle and the data is exclusive in the third level cache, the data is provided directly from the third level cache, without requiring an access to main memory, reducing the use of the host bus.
摘要:
A computer card comprising a first connector to enable the computer card to communicatively couple to an electronic device when the computer card is inserted into an externally accessible slot of the electronic device. The computer card further comprising an expansion slot configured to receive an expansion card therein. The computer card further comprising a second connector to facilitate coupling of a peripheral device to the computer card.
摘要:
A computer card comprising a first connector to enable the computer card to communicatively couple to an electronic device when the computer card is inserted into an externally accessible slot of the electronic device. The computer card further comprising an expansion slot configured to receive an expansion card therein. The computer card further comprising a second connector to facilitate coupling of a peripheral device to the computer card.
摘要:
A computer system reroutes a configuration cycle intended for an unused system bus address line to the IDSEL, or equivalent, configuration chip select input pin of a device which uses the same system bus address line as another device on the system bus. The computer system has a PCI bus to which a programmable logic device and an electronically-controlled switch are connected. The programmable logic device detects PCI bus configuration cycles associated with a PCI bus AD line that is otherwise unused as a chip select during configuration cycles. When the logic device detects a configuration cycle associated with the unused AD line, the logic device asserts a control signal to the electronically-controlled switch. The switch then connects the previously unused AD line to the AD line that is connected to the IDSEL input pin of the PCI device that experiences the conflict. The PCI device then effectively responds to the configuration read or write cycle as if its IDSEL input pin was hardwired to the switched AD line.
摘要:
There is provided a method of providing secure access to data stored in a system memory of a computer system, the computer system comprising a memory controller for writing data to and reading data from the system memory. The method comprises generating a random encryption key each time the computer system is booted and storing the random encryption key in a volatile memory region of the memory controller. The method additionally comprises encrypting data using the random encryption key to create encrypted data, and storing the encrypted data in the system memory. Also provided are a memory subsystem and a computer system for performing the method.
摘要:
An electronic device thermal management system comprising a thermal management controller configured to maintain a temperature level within a housing of an electronic device based on a signal indicative of a temperature of at least a portion of a wall of the housing of the electronic device.