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    System and method for providing secure access to system memory
    1.
    发明授权
    System and method for providing secure access to system memory 有权
    提供对系统内存的安全访问的系统和方法

    公开(公告)号：US09251358B2

    公开(公告)日：2016-02-02

    申请号：US12991861

    申请日：2008-05-09

    申请人： Walter G. Fry ,  Valiuddin Y. Ali ,  Manuel Novoa

    发明人： Walter G. Fry ,  Valiuddin Y. Ali ,  Manuel Novoa

    IPC分类号： G06F21/62 ,  G06F21/78

    CPC分类号： G06F21/62 ,  G06F21/78

    摘要： There is provided a method of providing secure access to data stored in a system memory of a computer system, the computer system comprising a memory controller for writing data to and reading data from the system memory. The method comprises generating a random encryption key each time the computer system is booted and storing the random encryption key in a volatile memory region of the memory controller. The method additionally comprises encrypting data using the random encryption key to create encrypted data, and storing the encrypted data in the system memory. Also provided are a memory subsystem and a computer system for performing the method.

    摘要翻译： 提供了一种提供对存储在计算机系统的系统存储器中的数据的安全访问的方法，所述计算机系统包括用于向系统存储器写入数据和从系统存储器读取数据的存储器控​​制器。 该方法包括在每次引导计算机系统时生成随机加密密钥，并将随机加密密钥存储在存储器控制器的易失性存储器区域中。 该方法另外包括使用随机加密密钥加密数据以创建加密数据，并将加密的数据存储在系统存储器中。 还提供了用于执行该方法的存储器子系统和计算机系统。

    System And Method For Providing Secure Access To System Memory
    2.
    发明申请
    System And Method For Providing Secure Access To System Memory 有权
    系统和方法为系统内存提供安全访问

    公开(公告)号：US20110064217A1

    公开(公告)日：2011-03-17

    申请号：US12991861

    申请日：2008-05-09

    申请人： Walter G. Fry ,  Ali Y. Valiuddin ,  Manuel Novoa

    发明人： Walter G. Fry ,  Ali Y. Valiuddin ,  Manuel Novoa

    IPC分类号： H04L9/26 ,  G06F15/177

    CPC分类号： G06F21/62 ,  G06F21/78

    摘要： There is provided a method of providing secure access to data stored in a system memory of a computer system, the computer system comprising a memory controller for writing data to and reading data from the system memory. The method comprises generating a random encryption key each time the computer system is booted and storing the random encryption key in a volatile memory region of the memory controller. The method additionally comprises encrypting data using the random encryption key to create encrypted data, and storing the encrypted data in the system memory. Also provided are a memory subsystem and a computer system for performing the method.

    摘要翻译： 提供了一种提供对存储在计算机系统的系统存储器中的数据的安全访问的方法，所述计算机系统包括用于向系统存储器写入数据和从系统存储器读取数据的存储器控​​制器。 该方法包括在每次引导计算机系统时生成随机加密密钥，并将随机加密密钥存储在存储器控制器的易失性存储器区域中。 该方法另外包括使用随机加密密钥加密数据以创建加密数据，并将加密的数据存储在系统存储器中。 还提供了用于执行该方法的存储器子系统和计算机系统。

    THREE-DIMENSIONAL COMPUTER INTERFACE
    3.
    发明申请
    THREE-DIMENSIONAL COMPUTER INTERFACE 审中-公开
    三维计算机界面

    公开(公告)号：US20130009875A1

    公开(公告)日：2013-01-10

    申请号：US13177472

    申请日：2011-07-06

    申请人： Walter G. Fry ,  William A. Curtis

    发明人： Walter G. Fry ,  William A. Curtis

    IPC分类号： G06F3/042 ,  G06F3/02

    CPC分类号： G06F3/017 ,  G06F3/0304

    摘要： Techniques are disclosed relating to a three-dimensional computer interface. In one embodiment, an apparatus is disclosed that includes a camera and a proximity sensor. The camera is configured to capture an image that includes an object. In some embodiments, the proximity sensor is configured to perform a measurement operation that includes determining only a single distance value for the object. The apparatus is configured to calculate a location of the object based on the captured image and the single distance value. In some embodiments, the apparatus is configured to determine a motion of the object by calculating a plurality of locations of the object. In some embodiments, the apparatus is configured to identify the object as a user's hand, and to control a depiction of content on a display based on the determined path of motion for the user's hand.

    摘要翻译： 公开了涉及三维计算机接口的技术。 在一个实施例中，公开了一种包括相机和接近传感器的装置。 相机配置为捕获包含对象的图像。 在一些实施例中，接近传感器被配置为执行包括仅确定对象的单个距离值的测量操作。 该装置被配置为基于所捕获的图像和单个距离值来计算对象的位置。 在一些实施例中，该装置被配置为通过计算对象的多个位置来确定对象的运动。 在一些实施例中，该装置被配置为基于用户的手的确定的运动路径来将对象识别为用户的手，并且控制对显示器上的内容的描绘。

    Processor board having a second level writeback cache system and a third level writethrough cache system which stores exclusive state information for use in a multiprocessor computer system
    4.
    发明授权
    Processor board having a second level writeback cache system and a third level writethrough cache system which stores exclusive state information for use in a multiprocessor computer system 失效
    具有第二级回写缓存系统的处理器板和存储用于多处理器计算机系统中的独占状态信息的第三级写入高速缓存系统

    公开(公告)号：US5561779A

    公开(公告)日：1996-10-01

    申请号：US237779

    申请日：1994-05-04

    申请人： Michael T. Jackson ,  Walter G. Fry

    发明人： Michael T. Jackson ,  Walter G. Fry

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0811 ,  G06F12/0831

    摘要： A computer system which utilizes processor boards including a first level cache system integrated with the microprocessor, a second level external cache system and a third level external cache system. The second level cache system is a conventional, high speed, SRAM-based, writeback cache system. The third level cache system is a large, writethrough cache system developed using conventional DRAMs as used in the main memory subsystem of the computer system. The three cache systems are arranged between the CPU and the host bus in a serial fashion. Because of the large size of the third level cache, a high hit rate is developed so that operations are not executed on the host bus but are completed locally on the processor board, reducing the use of the host bus by an individual processor board. This allows additional processor boards to be installed in the computer system without saturating the host bus. The third level cache system is organized as a writethrough cache. However, the shared or exclusive status of any cached data is also stored. If the second level cache performs a write allocate cycle and the data is exclusive in the third level cache, the data is provided directly from the third level cache, without requiring an access to main memory, reducing the use of the host bus.

    摘要翻译： 一种使用处理器板的计算机系统，其包括与微处理器集成的第一级高速缓存系统，第二级外部高速缓存系统和第三级外部高速缓存系统。 第二级缓存系统是传统的基于SRAM的高速缓存系统。 第三级缓存系统是使用传统DRAM开发的大型写入式缓存系统，如在计算机系统的主存储器子系统中所使用的那样。 三个缓存系统以串行方式布置在CPU和主机总线之间。 由于第三级缓存的大尺寸，所以开发出高命中率，使得在主机总线上不执行操作，而是在处理器板本地完成操作，从而减少单个处理器板使用主机总线。 这允许在计算机系统中安装额外的处理器板，而不会使主机总线饱和。 第三级缓存系统被组织为写入缓存。 但是，也存储任何缓存数据的共享或排他状态。 如果第二级缓存执行写分配周期并且数据在第三级高速缓存中是排他性的，则直接从第三级高速缓存提供数据，而不需要访问主存储器，从而减少主机总线的使用。

    Method and apparatus for concurrency of bus operations
    5.
    发明授权
    Method and apparatus for concurrency of bus operations 失效
    总线运行并发的方法和装置

    公开(公告)号：US5353415A

    公开(公告)日：1994-10-04

    申请号：US955477

    申请日：1992-10-02

    申请人： Jeff W. Wolford ,  Walter G. Fry

    发明人： Jeff W. Wolford ,  Walter G. Fry

    IPC分类号： G06F12/08 ,  G06F13/00

    CPC分类号： G06F12/0831

    摘要： A method and apparatus for performing concurrent operations on the host bus, expansion bus, and local I/O bus as well as the processor bus connecting the processor and cache system to increase computer system efficiency. A plurality of CPU boards are coupled to a host bus which in turn is coupled to an expansion bus through a bus controller. Each CPU board includes a processor connected to a cache system including a cache controller and cache memory. The cache system interfaces to the host bus through address and data buffers controlled by cache interface logic. Distributed system peripheral (DSP) logic comprising various ports, timers, and interrupt controller logic is coupled to the cache system, data buffers, and cache interface logic by a local I/O bus. The computer system supports various areas of concurrent operation, including concurrent local I/O cycles, host bus snoop cycles and CPU requests, as well as concurrent expansion bus reads with snooped host bus cycles.

    摘要翻译： 一种在主机总线，扩展总线和本地I / O总线上执行并行操作的方法和装置，以及连接处理器和缓存系统的处理器总线，以提高计算机系统的效率。 多个CPU板耦合到主机总线，主机总线又通过总线控制器耦合到扩展总线。 每个CPU板包括连接到包括高速缓存控制器和高速缓冲存储器的高速缓存系统的处理器。 缓存系统通过由缓存接口逻辑控制的地址和数据缓冲器与主机总线进行接口。 包括各种端口，定时器和中断控制器逻辑的分布式系统外设（DSP）逻辑由本地I / O总线耦合到高速缓存系统，数据缓冲器和高速缓存接口逻辑。 计算机系统支持并行操作的各个领域，包括并发本地I / O周期，主机总线侦听周期和CPU请求以及带有主机总线周期的并发扩展总线读取。

    Dynamic PCI device identification redirection on a configuration space access conflict
    8.
    发明授权
    Dynamic PCI device identification redirection on a configuration space access conflict 失效
    动态PCI设备识别重定向在配置空间访问冲突

    公开(公告)号：US06636904B2

    公开(公告)日：2003-10-21

    申请号：US09443687

    申请日：1999-11-18

    申请人： Walter G. Fry ,  Robert E. Krancher ,  Richard S. Lin

    发明人： Walter G. Fry ,  Robert E. Krancher ,  Richard S. Lin

    IPC分类号： G06F300

    CPC分类号： G06F13/4004 ,  G06F2213/0024

    摘要： A computer system reroutes a configuration cycle intended for an unused system bus address line to the IDSEL, or equivalent, configuration chip select input pin of a device which uses the same system bus address line as another device on the system bus. The computer system has a PCI bus to which a programmable logic device and an electronically-controlled switch are connected. The programmable logic device detects PCI bus configuration cycles associated with a PCI bus AD line that is otherwise unused as a chip select during configuration cycles. When the logic device detects a configuration cycle associated with the unused AD line, the logic device asserts a control signal to the electronically-controlled switch. The switch then connects the previously unused AD line to the AD line that is connected to the IDSEL input pin of the PCI device that experiences the conflict. The PCI device then effectively responds to the configuration read or write cycle as if its IDSEL input pin was hardwired to the switched AD line.

    摘要翻译： 计算机系统将用于未使用的系统总线地址线的配置周期重新路由到使用与系统总线上的另一个设备相同的系统总线地址线的设备的IDSEL或等效的配置芯片选择输入引脚。 计算机系统具有连接可编程逻辑器件和电子控制开关的PCI总线。 可编程逻辑器件检测与PCI总线AD线相关联的PCI总线配置周期，否则在配置周期期间作为芯片选择而不使用PCI总线配置周期。 当逻辑器件检测到与未使用的AD线路相关联的配置周期时，逻辑器件向电子控制开关断言控制信号。 然后，交换机将先前未使用的AD线路连接到连接到经历冲突的PCI设备的IDSEL输入引脚的AD线路。 PCI设备然后可有效地响应配置读或写周期，就好像其IDSEL输入引脚与连接的AD线硬连线一样。

    Electronic device thermal management system and method
    9.
    发明授权
    Electronic device thermal management system and method 有权
    电子设备热管理系统及方法

    公开(公告)号：US08798806B2

    公开(公告)日：2014-08-05

    申请号：US11799185

    申请日：2007-04-30

    申请人： Jeffrey A. Lev ,  Jeffrey Kevin Jeansonne ,  Walter G. Fry

    发明人： Jeffrey A. Lev ,  Jeffrey Kevin Jeansonne ,  Walter G. Fry

    IPC分类号： G05D23/00

    CPC分类号： G05D23/19

    摘要： An electronic device thermal management system comprising a thermal management controller configured to maintain a temperature level within a housing of an electronic device based on a signal indicative of a temperature of at least a portion of a wall of the housing of the electronic device.

    摘要翻译： 一种电子设备热管理系统，包括热管理控制器，其被配置为基于指示电子设备的壳体的壁的至少一部分的温度的信号来将电子设备的壳体内的温度水平维持在电子设备的壳体内。