Variable clocking read capture for double data rate memory devices
    5.
    发明授权
    Variable clocking read capture for double data rate memory devices 有权
    双数据速率存储器件的可变时钟读取捕获

    公开(公告)号:US07499368B2

    公开(公告)日:2009-03-03

    申请号:US11052371

    申请日:2005-02-07

    IPC分类号: G11C8/00

    CPC分类号: G11C7/22 G11C7/1066 G11C7/222

    摘要: A system comprising a first double data rate (DDR) memory device, a second DDR memory device coupled to the first DDR memory device, the second DDR memory device not using a delay locked loop (DLL) device to synchronize clock signals. The system further comprises a logic coupled to the first and second DDR memory devices. The logic is adapted to receive data from the first and second DDR memory devices by way of a single conductive pathway.

    摘要翻译: 一种包括第一双数据速率(DDR)存储器设备,耦合到第一DDR存储器设备的第二DDR存储器设备,不使用延迟锁定环(DLL)设备来同步时钟信号的第二DDR存储器设备的系统。 该系统还包括耦合到第一和第二DDR存储器件的逻辑。 该逻辑适于通过单个导电路径从第一和第二DDR存储器设备接收数据。