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    Context switch instruction prefetching in multithreaded computer
    1.
    发明申请
    Context switch instruction prefetching in multithreaded computer 失效
    多线程计算机中的上下文切换指令预取

    公开(公告)号：US20050138628A1

    公开(公告)日：2005-06-23

    申请号：US10739739

    申请日：2003-12-18

    申请人： Jeffrey Bradford ,  Harold Kossman ,  Timothy Mullins

    发明人： Jeffrey Bradford ,  Harold Kossman ,  Timothy Mullins

    IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F12/08

    CPC分类号： G06F9/3802 ,  G06F9/3851 ,  G06F12/0842 ,  G06F12/0862

    摘要： An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of at least one instruction likely to be executed by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, one or more instructions may be prefetched on behalf of that thread so that when execution of the thread is resumed, those instructions are more likely to be cached, or at least in the process of being retrieved into cache memory, thus enabling a thread to begin executing instructions more quickly than if the thread was required to fetch those instructions upon resumption of its execution.

    摘要翻译： 一种装置，程序产品和方法结合上下文切换操作，在恢复该线程的执行之前启动可能被线程执行的至少一个指令的预取。 因此，一旦知道将对特定线程执行上下文切换，则可以代表该线程预取一个或多个指令，使得当线程的执行被恢复时，这些指令更可能被缓存 或者至少在被检索到高速缓冲存储器的过程中，因此使得线程比在恢复其执行时要求线程获取那些指令时更快地开始执行指令。

    Reconfiguring caches to support metadata for polymorphism
    3.
    发明申请
    Reconfiguring caches to support metadata for polymorphism 审中-公开
    重新配置缓存以支持多态性的元数据

    公开(公告)号：US20070083711A1

    公开(公告)日：2007-04-12

    申请号：US11246818

    申请日：2005-10-07

    申请人： Jeffrey Bradford ,  Richard Eickemeyer ,  Timothy Heil ,  Harold Kossman ,  Timothy Mullins

    发明人： Jeffrey Bradford ,  Richard Eickemeyer ,  Timothy Heil ,  Harold Kossman ,  Timothy Mullins

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0893

    摘要： In a method of using a cache in a computer, the computer is monitored to detect an event that indicates that the cache is to be reconfigured into a metadata state. When the event is detected, the cache is reconfigured so that a predetermined portion of the cache stores metadata. A computational circuit employed in association with a computer includes a cache, a cache event detector circuit, and a cache reconfiguration circuit. The cache event detector circuit detects an event relative to the cache. The cache reconfiguration circuit reconfigures the cache so that a predetermined portion of the cache stores metadata when the cache event detector circuit detects the event.

    摘要翻译： 在计算机中使用高速缓存的方法中，监视计算机以检测指示将高速缓存重新配置为元数据状态的事件。 当检测到事件时，重新配置高速缓存，使得高速缓存的预定部分存储元数据。 与计算机相关联地使用的计算电路包括高速缓存，高速缓存事件检测器电路和高速缓存重配置电路。 高速缓存事件检测器电路检测相对于高速缓存的事件。 高速缓存重配置电路重新配置高速缓存，使得当高速缓存事件检测器电路检测到事件时，高速缓存的预定部分存储元数据。

    Context switch data prefetching in multithreaded computer
    5.
    发明申请
    Context switch data prefetching in multithreaded computer 失效
    多线程计算机中的上下文切换数据预取

    公开(公告)号：US20050138627A1

    公开(公告)日：2005-06-23

    申请号：US10739738

    申请日：2003-12-18

    申请人： Jeffrey Bradford ,  Harold Kossman ,  Timothy Mullins

    发明人： Jeffrey Bradford ,  Harold Kossman ,  Timothy Mullins

    IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F12/08

    CPC分类号： G06F9/463 ,  G06F12/0862 ,  G06F2212/6028

    摘要： An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, data may be prefetched on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory, thus reducing cache-related performance penalties associated with context switching.

    摘要翻译： 一种装置，程序产品和方法结合上下文切换操作，在恢复该线程的执行之前启动可能由线程使用的数据的预取。 因此，一旦知道将对特定线程执行上下文切换，则可以代表该线程预取数据，使得当线程的执行被恢复时，线程的更多的工作状态可能 被缓存，或至少在被检索到高速缓冲存储器的过程中，从而减少与上下文切换相关联的与缓存相关的性能惩罚。