DYNAMIC DATA COMPRESSION SYSTEM
    1.
    发明申请
    DYNAMIC DATA COMPRESSION SYSTEM 审中-公开
    动态数据压缩系统

    公开(公告)号:US20150006667A1

    公开(公告)日:2015-01-01

    申请号:US13930134

    申请日:2013-06-28

    IPC分类号: H04L29/08

    摘要: This disclosure is directed to a dynamic data compression system. A device may request data comprising certain content from a remote resource. The remote resource may determine if any part of the content is identical or similar to content in other data and if the other data is already on the requesting device. Smart compression may then involve transmitting only the portions of the content not residing on the requesting device, which may combine the received portions of the content with the other data. In another example, a capturing device may capture at least one of an image or video. Smart compression may then involve transmitting only certain features of the image/video to the remote resource. The remote resource may determine image/video content based on the received features, and may perform an action based on the content. In addition, a determination whether to perform smart compression may be based on system/device conditions.

    摘要翻译: 本公开涉及动态数据压缩系统。 设备可以从远程资源请求包括某些内容的数据。 远程资源可以确定内容的任何部分是否与其他数据中的内容相同或相似,并且其他数据是否已经在请求设备上。 然后,智能压缩可以仅涉及仅发送不驻留在请求设备上的内容的部分,其可以将接收的内容部分与其他数据组合。 在另一示例中,捕获设备可以捕获图像或视频中的至少一个。 智能压缩可能仅涉及将图像/视频的某些特征仅发送到远程资源。 远程资源可以基于接收到的特征来确定图像/视频内容,并且可以基于内容执行动作。 此外,是否执行智能压缩的确定可以基于系统/设备条件。

    Apparatus and Method For Reducing The Flushing Time Of A Cache
    2.
    发明申请
    Apparatus and Method For Reducing The Flushing Time Of A Cache 有权
    用于降低高速缓存冲洗时间的装置和方法

    公开(公告)号:US20140095794A1

    公开(公告)日:2014-04-03

    申请号:US13631625

    申请日:2012-09-28

    IPC分类号: G06F12/08

    CPC分类号: G06F12/08 G06F12/0891

    摘要: A processor is described having cache circuitry and logic circuitry. The logic circuitry is to manage the entry and removal of cache lines from the cache circuitry. The logic circuitry includes storage circuitry and control circuitry. The storage circuitry is to store information identifying a set of cache lines within the cache that are in a modified state. The control circuitry is coupled to the storage circuitry to receive the information from the storage circuitry, responsive to a signal to flush the cache, and determine addresses of the cache therefrom so that the set of cache lines are read from the cache so as to avoid reading cache lines from the cache that are in an invalid or a clean state.

    摘要翻译: 描述了具有高速缓存电路和逻辑电路的处理器。 逻辑电路是管理高速缓存线路的高速缓存行的输入和移除。 逻辑电路包括存储电路和控制电路。 存储电路用于存储标识高速缓存中处于修改状态的一组高速缓存行的信息。 控制电路耦合到存储电路,以响应于刷新高速缓存的信号从存储电路接收信息,并从其中确定高速缓存的地址,从而从高速缓存读取高速缓存行集合,以避免 从缓存中读取处于无效或干净状态的缓存行。