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公开(公告)号：US07053901B2
公开(公告)日：2006-05-30
申请号：US10732445
申请日：2003-12-11
申请人： Jen-Hsun Huang , Michael Brian Cox , Ziyad S. Hakura , John S. Montrym , Brad W. Simeral , Brian Keith Langendorf , Blanton Scott Kephart , Franck R. Diard
发明人： Jen-Hsun Huang , Michael Brian Cox , Ziyad S. Hakura , John S. Montrym , Brad W. Simeral , Brian Keith Langendorf , Blanton Scott Kephart , Franck R. Diard
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06T15/005
摘要： Embodiments of the invention accelerate at least one special purpose processor, such as a GPU, or a driver managing a special purpose processor, by using at least one co-processor. Advantageously, embodiments of the invention are fault-tolerant in that the at least one GPU or other special purpose processor is able to execute all computations, although perhaps at a lower level of performance, if the at least one co-processor is rendered inoperable. The co-processor may also be used selectively, based on performance considerations.
摘要翻译： 本发明的实施例通过使用至少一个协处理器来加速至少一个专用处理器，例如GPU，或者管理专用处理器的驱动器。 有利地，本发明的实施例是容错的，因为如果使至少一个协处理器变得不可操作，则至少一个GPU或其他专用处理器能够执行所有计算，尽管可能处于较低的性能水平。 可以基于性能考虑，有选择地使用协处理器。
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公开(公告)号：US07755624B1
公开(公告)日：2010-07-13
申请号：US12266820
申请日：2008-11-07
CPC分类号： G06T15/005 , G06T15/405
摘要： A processor generates Z-cull information for tiles and groups of tiles. In one embodiment the processor includes an on-chip cache to coalesce Z information for tiles to identify occluded tiles. In a coprocessor embodiment, the processor provides Z-culling information to a graphics processor.
摘要翻译： 处理器生成瓦片和瓦片组的Z-cull信息。 在一个实施例中，处理器包括片上高速缓存以合并瓦片的Z信息以识别封闭的瓦片。 在协处理器实施例中，处理器向图形处理器提供Z剔除信息。
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公开(公告)号：US07450120B1
公开(公告)日：2008-11-11
申请号：US10741115
申请日：2003-12-19
CPC分类号： G06T15/005 , G06T15/405
摘要： A processor generates Z-cull information for tiles and groups of tiles. In one embodiment the processor includes an on-chip cache to coalesce Z information for tiles to identify occluded tiles. In a coprocessor embodiment, the processor provides Z-culling information to a graphics processor.
摘要翻译： 处理器生成瓦片和瓦片组的Z-cull信息。 在一个实施例中，处理器包括片上高速缓存以合并瓦片的Z信息以识别封闭的瓦片。 在协处理器实施例中，处理器向图形处理器提供Z剔除信息。
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公开(公告)号：US07920701B1
公开(公告)日：2011-04-05
申请号：US11304408
申请日：2005-12-14
IPC分类号： H04N7/167
CPC分类号： H04N21/4367 , H04N21/42646 , H04N21/4325 , H04N21/4405 , H04N21/4408
摘要： A digital content system is disclosed. A security engine disposed in a bridge provides cryptographic services. Clear text digital data received from a central processing unit is encrypted and transferred via the bridge over unsecured data paths as cipher text.
摘要翻译： 公开了数字内容系统。 布置在桥中的安全引擎提供加密服务。 从中央处理单元接收到的清除文本数字数据被加密并通过不安全数据路径作为密文通过桥传输。
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5.发明授权Chipset support for non-uniform memory access among heterogeneous processing units 有权芯片组支持异构处理单元之间的非均匀内存访问公开(公告)号：US09015446B2
公开(公告)日：2015-04-21
申请号：US12332016
申请日：2008-12-10
申请人： Michael Brian Cox , Brad W. Simeral
发明人： Michael Brian Cox , Brad W. Simeral
CPC分类号： G06F12/0284 , G06F12/1081
摘要： A method for providing a first processor access to a memory associated with a second processor. The method includes receiving a first address map from the first processor that includes an MMIO aperture for a NUMA device, receiving a second address map from a second processor that includes MMIO apertures for hardware devices that the second processor is configured to access, and generating a global address map by combining the first and second address maps. The method further includes receiving an access request transmitted from the first processor to the NUMA device, generating a memory access request based on the first access request and a translation table that maps a first address associated with the first access request into a second address associated with the memory associated with the second processor, and routing the memory access request to the memory based on the global address map.
摘要翻译： 一种用于提供对与第二处理器相关联的存储器的第一处理器访问的方法。 该方法包括从第一处理器接收包括用于NUMA设备的MMIO孔径的第一地址映射，从包括第二处理器被配置为访问的硬件设备的MMIO孔径的第二处理器接收第二地址映射，并且生成 通过组合第一和第二地址映射的全局地址映射。 该方法还包括接收从第一处理器发送到NUMA设备的接入请求，基于第一接入请求生成存储器访问请求，以及将与第一接入请求相关联的第一地址映射到与第一接入请求相关联的第二地址的转换表 与第二处理器相关联的存储器，以及基于全局地址映射将存储器访问请求路由到存储器。
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6.发明申请公开(公告)号：US20120304285A1
公开(公告)日：2012-11-29
申请号：US13568023
申请日：2012-08-06
申请人： Brad W. Simeral , Michael Brian Cox
发明人： Brad W. Simeral , Michael Brian Cox
IPC分类号： G06F21/00
CPC分类号： G06F9/45537
摘要： A method for providing an operating system access to devices, including enumerating hardware devices and virtualized devices, where resources associated with a first hardware device are divided into guest physical resources creating a software virtualized device, and multiple instances of resources associated with a second hardware device are advertised thereby creating a hardware virtualized device. First and second permission lists are generated that specify which operating systems are permitted to access the software virtualized device and the hardware virtualized device, respectively. First and second sets of virtual address maps are generated, where each set maps an address space associated with either the software virtualized device or the hardware virtualized device into an address space associated with each operating system included in the corresponding permission list. The method further includes arbitrating access requests from each of the plurality of operating systems based on the permission lists and the virtual address maps.
摘要翻译： 一种用于提供对包括枚举硬件设备和虚拟化设备的枚举的设备的操作系统访问的方法，其中与第一硬件设备相关联的资源被划分为创建软件虚拟化设备的客户物理资源以及与第二硬件设备相关联的资源的多个实例 由此创建一个硬件虚拟化设备。 生成第一和第二权限列表，其指定哪些操作系统被允许访问软件虚拟化设备和硬件虚拟化设备。 生成第一和第二组虚拟地址映射，其中每个集合将与软件虚拟化设备或硬件虚拟化设备相关联的地址空间映射到与包括在相应的许可列表中的每个操作系统相关联的地址空间中。 该方法还包括基于许可列表和虚拟地址映射来仲裁来自多个操作系统中的每一个的访问请求。
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7.发明授权Chipset support for binding and migrating hardware devices among heterogeneous processing units 有权芯片组支持在异构处理单元之间绑定和迁移硬件设备公开(公告)号：US09032101B1
公开(公告)日：2015-05-12
申请号：US12332009
申请日：2008-12-10
申请人： Michael Brian Cox , Brad W. Simeral
发明人： Michael Brian Cox , Brad W. Simeral
CPC分类号： G06F12/1081 , G06F12/0292 , G06F12/0692 , G06F2212/206
摘要： A method for providing access to hardware devices by a processor without causing conflicts with other processors included in a computer system. The method includes receiving a first address map from a first processor and a second address map from a second processor, where each address map includes memory-mapped input/output (I/O) apertures for a set of hardware devices that the processor is configured to access. The method further includes generating a global address map by combining the first address map and the second address map, receiving a first access request from the first processor and routing the first access request to a hardware device based on an address mapping included in the global address map. Advantageously, heterogeneous processors included in multi-processor system can access any hardware device included in the computer system, without modifying the processors, one or more operating systems executed by each processor, or the hardware devices.
摘要翻译： 一种用于通过处理器提供对硬件设备的访问的方法，而不引起与计算机系统中包括的其他处理器的冲突。 该方法包括从第一处理器接收第一地址映射和从第二处理器接收第二地址映射，其中每个地址映射包括处理器配置的一组硬件设备的存储器映射的输入/输出（I / O）孔径 访问。 该方法还包括通过组合第一地址映射和第二地址映射来生成全局地址映射，从第一处理器接收第一访问请求，并基于包含在全局地址中的地址映射将第一访问请求路由到硬件设备 地图。 有利地，包括在多处理器系统中的异构处理器可以访问包括在计算机系统中的任何硬件设备，而无需修改处理器，由每个处理器执行的一个或多个操作系统或硬件设备。
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8.发明授权公开(公告)号：US08943584B2
公开(公告)日：2015-01-27
申请号：US13568023
申请日：2012-08-06
申请人： Brad W. Simeral , Michael Brian Cox
发明人： Brad W. Simeral , Michael Brian Cox
CPC分类号： G06F9/45537
摘要： A method for providing an operating system access to devices, including enumerating hardware devices and virtualized devices, where resources associated with a first hardware device are divided into guest physical resources creating a software virtualized device, and multiple instances of resources associated with a second hardware device are advertised thereby creating a hardware virtualized device. First and second permission lists are generated that specify which operating systems are permitted to access the software virtualized device and the hardware virtualized device, respectively. First and second sets of virtual address maps are generated, where each set maps an address space associated with either the software virtualized device or the hardware virtualized device into an address space associated with each operating system included in the corresponding permission list. The method further includes arbitrating access requests from each of the plurality of operating systems based on the permission lists and the virtual address maps.
摘要翻译： 一种用于提供对包括枚举硬件设备和虚拟化设备的枚举的设备的操作系统访问的方法，其中与第一硬件设备相关联的资源被划分为创建软件虚拟化设备的客户物理资源以及与第二硬件设备相关联的资源的多个实例 由此创建一个硬件虚拟化设备。 生成第一和第二权限列表，其指定哪些操作系统被允许访问软件虚拟化设备和硬件虚拟化设备。 生成第一和第二组虚拟地址映射，其中每个集合将与软件虚拟化设备或硬件虚拟化设备相关联的地址空间映射到与包括在相应的许可列表中的每个操作系统相关联的地址空间中。 该方法还包括基于许可列表和虚拟地址映射来对来自多个操作系统中的每一个的访问请求进行仲裁。
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9.发明申请公开(公告)号：US20100146620A1
公开(公告)日：2010-06-10
申请号：US12330466
申请日：2008-12-08
申请人： Brad W. Simeral , Michael Brian Cox
发明人： Brad W. Simeral , Michael Brian Cox
IPC分类号： G06F21/22
CPC分类号： G06F9/45537
摘要： A method for providing an operating system access to devices, including enumerating hardware devices and virtualized devices, where resources associated with a first hardware device are divided into guest physical resources creating a software virtualized device, and multiple instances of resources associated with a second hardware device are advertised thereby creating a hardware virtualized device. First and second permission lists are generated that specify which operating systems are permitted to access the software virtualized device and the hardware virtualized device, respectively. First and second sets of virtual address maps are generated, where each set maps an address space associated with either the software virtualized device or the hardware virtualized device into an address space associated with each operating system included in the corresponding permission list. The method further includes arbitrating access requests from each of the plurality of operating systems based on the permission lists and the virtual address maps.
摘要翻译： 一种用于提供对包括枚举硬件设备和虚拟化设备的枚举的设备的操作系统访问的方法，其中与第一硬件设备相关联的资源被划分为创建软件虚拟化设备的客户物理资源以及与第二硬件设备相关联的资源的多个实例 由此创建一个硬件虚拟化设备。 生成第一和第二权限列表，其指定哪些操作系统被允许访问软件虚拟化设备和硬件虚拟化设备。 生成第一和第二组虚拟地址映射，其中每个集合将与软件虚拟化设备或硬件虚拟化设备相关联的地址空间映射到与包括在相应的许可列表中的每个操作系统相关联的地址空间中。 该方法还包括基于许可列表和虚拟地址映射来对来自多个操作系统中的每一个的访问请求进行仲裁。
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公开(公告)号：US07289125B2
公开(公告)日：2007-10-30
申请号：US10789248
申请日：2004-02-27
CPC分类号： G06F3/14 , G06F3/1438 , G06T1/20 , G06T15/005 , G09G5/363
摘要： A bridge associated with a broadcast aperture facilitates the transfer of rendering commands and data between a processor and multiple graphics devices. The bridge receives data written by the processor to the broadcast aperture and forwards it to multiple graphics devices, eliminating the need for the processor to perform duplicative(?) write operations. During system initialization, a broadcast aperture is allocated to the bridge in address space based on an aperture size value set using a system configuration utility and stored in system configuration memory. A graphics driver activates the broadcast aperture by sending unicast aperture parameters associated with the multiple graphics devices to the bridge via a bridge driver. Upon activating the broadcast aperture, multiple graphics devices can be operated in parallel to improve rendering performance. Parallel rendering techniques include split-frame, alternate frame, and combined split- and alternate frame rendering.
摘要翻译： 与广播孔径相关联的桥接器有助于在处理器和多个图形设备之间传送渲染命令和数据。 桥接器将处理器写入的数据接收到广播孔径并将其转发到多个图形设备，从而无需处理器执行重复（？）写入操作。 在系统初始化期间，基于使用系统配置实用程序设置的存储在系统配置存储器中的孔径大小值，将广播孔径分配给地址空间中的桥。 图形驱动器通过经由桥驱动器将与多个图形设备相关联的单播孔径参数发送到桥接器来激活广播孔径。 在激活广播孔径时，可以并行地操作多个图形设备以提高渲染性能。 并行渲染技术包括分割帧，备用帧以及组合分割和交替帧渲染。
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