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公开(公告)号：US07289125B2
公开(公告)日：2007-10-30
申请号：US10789248
申请日：2004-02-27
CPC分类号： G06F3/14 , G06F3/1438 , G06T1/20 , G06T15/005 , G09G5/363
摘要： A bridge associated with a broadcast aperture facilitates the transfer of rendering commands and data between a processor and multiple graphics devices. The bridge receives data written by the processor to the broadcast aperture and forwards it to multiple graphics devices, eliminating the need for the processor to perform duplicative(?) write operations. During system initialization, a broadcast aperture is allocated to the bridge in address space based on an aperture size value set using a system configuration utility and stored in system configuration memory. A graphics driver activates the broadcast aperture by sending unicast aperture parameters associated with the multiple graphics devices to the bridge via a bridge driver. Upon activating the broadcast aperture, multiple graphics devices can be operated in parallel to improve rendering performance. Parallel rendering techniques include split-frame, alternate frame, and combined split- and alternate frame rendering.
摘要翻译： 与广播孔径相关联的桥接器有助于在处理器和多个图形设备之间传送渲染命令和数据。 桥接器将处理器写入的数据接收到广播孔径并将其转发到多个图形设备，从而无需处理器执行重复（？）写入操作。 在系统初始化期间，基于使用系统配置实用程序设置的存储在系统配置存储器中的孔径大小值，将广播孔径分配给地址空间中的桥。 图形驱动器通过经由桥驱动器将与多个图形设备相关联的单播孔径参数发送到桥接器来激活广播孔径。 在激活广播孔径时，可以并行地操作多个图形设备以提高渲染性能。 并行渲染技术包括分割帧，备用帧以及组合分割和交替帧渲染。
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公开(公告)号：US08635480B1
公开(公告)日：2014-01-21
申请号：US12037879
申请日：2008-02-26
申请人： Ludger Mimberg , David G. Reed , David Wyatt , Gary D. Hicok , Rambod Jacoby
发明人： Ludger Mimberg , David G. Reed , David Wyatt , Gary D. Hicok , Rambod Jacoby
IPC分类号： G06F1/32
CPC分类号： G06F1/3293 , G06F1/325 , G06F1/3287 , G09G5/363 , G09G2360/08 , G09G2370/12 , Y02D10/122 , Y02D10/171 , Y02D50/20
摘要： In a computer system with multiple processing units, power to one or more of the processing units is turned off while the other processing units remain powered on. The processing unit that is powered off may be a GPU on a graphics adapter card, and power to this GPU is controlled by turning on and off the power supplied through a voltage regulator. With this configuration, power to the GPU on the graphics adapter card can be turned off when it is not in use or when it is being used for graphics processing that another graphics processor can handle.
摘要翻译： 在具有多个处理单元的计算机系统中，对一个或多个处理单元的电力被关闭，而其他处理单元保持通电。 关闭的处理单元可以是图形适配器卡上的GPU，并且通过打开和关闭通过电压调节器提供的电力来控制对该GPU的电力。 使用此配置，图形适配器卡上的GPU的电源可以在不使用时被关闭，或者当它被用于另一个图形处理器可以处理的图形处理时被关闭。
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公开(公告)号：US07924868B1
公开(公告)日：2011-04-12
申请号：US11966659
申请日：2007-12-28
IPC分类号： H04L12/43
CPC分类号： H04L49/90 , H04L47/50 , H04L47/6225 , H04L49/109 , H04L49/602 , H04L49/901 , H04L63/0227 , H04L63/0428 , H04L63/08
摘要： A novel network architecture that integrates the functions of an Internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.
摘要翻译： 一种将互联网协议（IP）路由器的功能集成到驻留在主计算机芯片组中的网络处理单元（NPU）的新型网络架构，使得主计算机的资源被感知为单独的网络设备。 即使在一个实施例中它共享相同的芯片，NPU在逻辑上与主计算机分离。
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公开(公告)号：US07397797B2
公开(公告)日：2008-07-08
申请号：US10319791
申请日：2002-12-13
IPC分类号： H04L12/28
CPC分类号： H04L45/00 , H04L29/06 , H04L29/06027 , H04L45/60 , H04L63/0428 , H04L63/0485 , H04L63/08 , H04L63/164 , H04L65/4076 , H04L65/4084 , H04L69/04 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/166 , H04L69/22 , H04L69/32 , H04L2212/00
摘要： A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.
摘要翻译： 一种将互联网协议（IP）路由器的功能集成到驻留在主计算机芯片组中的网络处理单元（NPU）的新型网络架构，使得主计算机的资源被感知为单独的网络设备。 即使在一个实施例中它共享相同的芯片，NPU在逻辑上与主计算机分离。
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公开(公告)号：US5835104A
公开(公告)日：1998-11-10
申请号：US841360
申请日：1997-04-23
CPC分类号： G09G5/363 , G09G3/003 , G09G5/397 , G09G5/42 , G06F3/14 , G09G2310/04 , G09G2340/02 , G09G2360/02 , G09G5/022
摘要： A compositing buffer having an adjustable size and configuration reduces complexity and size of a multimedia processor integrated circuit. The compositing buffer may be optimized for lower resolutions, thus reducing its overall size and complexity, while still providing support for higher resolutions which may be required to support a particular standard. A pixel mapping logic receives data indicating the number of lines per band and number of pixels per line, as well as color depth (or any two of these data) and correctly maps compositing RAM bank access requests to the correct pixel location. In a second embodiment of the present invention, the variable band size of the compositing buffer may allow for an external memory to be used for a compositing buffer, for example, a portion of the display memory (frame buffer). While such an embodiment may reduce overall bandwidth, the associated cost reduction may make such an apparatus appealing for low cost applications. Band size may be adjusted depending upon pixel resolution and depth. In a third embodiment of the present invention, band size may be varied within a frame depending upon the number of layers or the complexity of each image portion. Simple portions of an image, have few layers, may be rendered using wide bands, whereas complex areas may be rendered in narrower bands.
摘要翻译： 具有可调节尺寸和配置的合成缓冲器降低了多媒体处理器集成电路的复杂度和尺寸。 合成缓冲区可以针对较低分辨率进行优化，从而降低其总体大小和复杂性，同时仍然支持可能需要支持特定标准的更高分辨率。 像素映射逻辑接收指示每行的行数和每行像素数的数据以及颜色深度（或这些数据中的任何两个），并将合并的RAM存储体访问请求正确地映射到正确的像素位置。 在本发明的第二实施例中，合成缓冲器的可变带宽可以允许将外部存储器用于合成缓冲器，例如显示存储器的一部分（帧缓冲器）。 虽然这样的实施例可以减少总体带宽，但是相关联的成本降低可能使得这种设备吸引低成本应用。 可以根据像素分辨率和深度来调节乐队的大小。 在本发明的第三实施例中，根据层的数量或每个图像部分的复杂度，可以在一个帧内改变带宽。 图像的简单部分，具有几层，可以使用宽带渲染，而复杂区域可以在较窄的带中呈现。
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6.发明授权Central processing unit data entering and interrogating device and method therefor 失效中央处理单元数据输入和询问装置及其方法
公开(公告)号：US5561761A
公开(公告)日：1996-10-01
申请号：US522856
申请日：1995-09-01
申请人： Gary D. Hicok , Judson A. Lehman , Thomas Alexander , Yong J. Lim , David R. Evoy , Yongmin Kim
发明人： Gary D. Hicok , Judson A. Lehman , Thomas Alexander , Yong J. Lim , David R. Evoy , Yongmin Kim
CPC分类号： G06F11/3656
摘要： A Central Processing Unit (CPU) debugging device and method therefor is disclosed which provides data entering and interrogating devices which will temporarily stop all CPU execution when desired by a user and allow a non-destructive intrusion into the contents of any of the CPU internal registers, state bits, and cache and local memories. After the desired CPU contents have been reviewed and subsequently altered or maintained by a user, the CPU execution may be resumed.
摘要翻译： 公开了一种中央处理单元（CPU）调试设备及其方法，其提供数据输入和询问设备，该设备将在用户需要时临时停止所有CPU执行，并允许非破坏性地入侵任何CPU内部寄存器的内容 ，状态位，缓存和本地存储器。 在所需的CPU内容已经被审查并随后被用户改变或维护之后，CPU执行可以被恢复。
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公开(公告)号：US08094670B1
公开(公告)日：2012-01-10
申请号：US11949734
申请日：2007-12-03
IPC分类号： H04L12/54
CPC分类号： H04L45/00 , H04L49/3009
摘要： A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.
摘要翻译： 一种将互联网协议（IP）路由器的功能集成到驻留在主计算机芯片组中的网络处理单元（NPU）的新型网络架构，使得主计算机的资源被感知为单独的网络设备。 即使在一个实施例中它共享相同的芯片，NPU在逻辑上与主计算机分离。
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8.发明授权公开(公告)号：US07362772B1
公开(公告)日：2008-04-22
申请号：US10319798
申请日：2002-12-13
IPC分类号： H04L12/54
CPC分类号： H04L45/00 , H04L49/3009
摘要： A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.
摘要翻译： 一种将互联网协议（IP）路由器的功能集成到驻留在主计算机芯片组中的网络处理单元（NPU）的新型网络架构，使得主计算机的资源被感知为单独的网络设备。 即使在一个实施例中它共享相同的芯片，NPU在逻辑上与主计算机分离。
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公开(公告)号：US07188250B1
公开(公告)日：2007-03-06
申请号：US10319376
申请日：2002-12-13
IPC分类号： H04L9/34
CPC分类号： H04L9/06 , H04L9/3236 , H04L63/0428 , H04L63/08 , H04L2209/043 , H04L2209/125 , H04L2209/20 , H04L2209/34 , H04L2209/60
摘要： A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.
摘要翻译： 一种将互联网协议（IP）路由器的功能集成到驻留在主计算机芯片组中的网络处理单元（NPU）的新型网络架构，使得主计算机的资源被感知为单独的网络设备。 即使在一个实施例中它共享相同的芯片，NPU在逻辑上与主计算机分离。
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公开(公告)号：US06266753B1
公开(公告)日：2001-07-24
申请号：US08890825
申请日：1997-07-10
IPC分类号： G06F1202
CPC分类号： G06F12/1081 , G06F12/1027 , G06F2212/401 , Y10S707/99942
摘要： A virtual memory manager for a multi-media engine allows individual media units to operate in their own virtual space in much the same way as a software program operating in virtual mode. The virtual memory controller performs address translation or mapping to the correct physical memory location (in local memory or system memory) and will also convert the data stream to or from a compressed format. In addition, the virtual memory controller provides a unified TLB (translation lookaside buffer) available to all media units. The TLB has four types of pointer entries which are controlled by two bits. The first bit controls whether the TLB entry is a direct map or a pointer to another translation table. the second bit controls whether the TLB entry is stored in a compressed format. The overall concept may allow dynamic load balancing between local media memory and system memory.
摘要翻译： 用于多媒体引擎的虚拟存储器管理器允许各个媒体单元以与以虚拟模式操作的软件程序大致相同的方式在其自己的虚拟空间中操作。 虚拟内存控制器执行地址转换或映射到正确的物理内存位置（在本地存储器或系统存储器中），并且还将数据流转换为压缩格式或从压缩格式转换。 此外，虚拟存储器控制器提供可用于所有媒体单元的统一TLB（翻译后备缓冲器）。 TLB有四种类型的指针条目，由两位控制。 第一个位控制TLB条目是直接映射还是指向另一个转换表的指针。 第二位控制TLB条目是否以压缩格式存储。 整体概念可以允许本地媒体存储器和系统存储器之间的动态负载平衡。
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