公开(公告)号：US20120044780A1

公开(公告)日：2012-02-23

申请号：US12983185

申请日：2010-12-31

Applicant: Yong Mi KIM ,  Jeong Hun LEE

Inventor： Yong Mi KIM ,  Jeong Hun LEE

IPC: G11C8/18

CPC classification number: G11C7/1057 ,  G11C7/1066 ,  G11C8/18

Abstract: A data output circuit of a semiconductor memory apparatus includes: a data control driver configured to drive rising data and falling data to output control rising data and control falling data or drive level data to output the control rising data and the control falling data, in response to an output level test signal; a DLL clock control unit configured to drive a rising clock and a falling clock to output a control rising clock and a control falling clock in response to an enable signal and the output level test signal; and a clock synchronization unit configured to synchronize the control rising data and the control falling data with the control rising clock and the control falling clock to output serial rising data and serial falling data.

Abstract translation: 半导体存储装置的数据输出电路包括：数据控制驱动器，被配置为驱动上升数据和下降数据以输出控制上升数据并控制下降数据或驱动电平数据以输出控制上升数据和控制下降数据 到输出电平测试信号; DLL时钟控制单元，被配置为响应于使能信号和输出电平测试信号驱动上升时钟和下降时钟以输出控制上升时钟和控制下降时钟; 以及时钟同步单元，被配置为使控制上升数据和控制下降数据与控制上升时钟和控制下降时钟同步，以输出串行上升数据和串行下降数据。

公开(公告)号：US20120204070A1

公开(公告)日：2012-08-09

申请号：US13366467

申请日：2012-02-06

Applicant: Jeong Hun LEE ,  Yong Mi KIM ,  Jeong Tae HWANG

Inventor： Jeong Hun LEE ,  Yong Mi KIM ,  Jeong Tae HWANG

IPC: G11C29/08 ,  G06F11/26

CPC classification number: G11C29/46

Abstract: A method of testing a semiconductor memory apparatus is provided. The data alignment units other than the one data align unit being tested are deactivated. Serial data is input to the activated data alignment unit to generate parallel data. The parallel data is decoded. A test mode signal corresponding to the decoded result is enabled to perform the test. Different serial data is input where the test mode signal is enabled to generate and decode parallel data. Both tests are then performed simultaneously based on a test mode signal corresponding to a result of the decoded parallel data.

Abstract translation: 提供一种测试半导体存储装置的方法。 除了被测试的一个数据对准单元之外的数据对准单元被去激活。 串行数据被输入到激活的数据对准单元以产生并行数据。 并行数据被解码。 与解码结果相对应的测试模式信号能够进行测试。 输入不同的串行数据，其中测试模式信号被使能以产生和解码并行数据。 然后基于与解码的并行数据的结果对应的测试模式信号同时执行两个测试。

公开(公告)号：US20120256675A1

公开(公告)日：2012-10-11

申请号：US13339158

申请日：2011-12-28

Applicant: Jeong Hun LEE

Inventor： Jeong Hun LEE

IPC: H03L5/00

CPC classification number: G11C5/147

Abstract: An integrated circuit includes: a reference voltage generation unit configured to be driven in response to an enable signal, select one of a plurality of reference voltages generated by dividing a power supply voltage as an input reference voltage, and output the input reference voltage; and a reference voltage level compensation unit configured to be driven in response to the enable signal and change a level of the input reference voltage by an amount of change in a level of an external voltage.

Abstract translation: 集成电路包括：参考电压生成单元，被配置为响应于使能信号被驱动，选择通过将电源电压除作为输入参考电压而产生的多个参考电压中的一个，并输出所述输入参考电压; 以及参考电压电平补偿单元，被配置为响应于所述使能信号被驱动，并且将所述输入参考电压的电平改变外部电压的电平的变化量。

公开(公告)号：US20120147679A1

公开(公告)日：2012-06-14

申请号：US13315483

申请日：2011-12-09

Applicant: Jeong Hun LEE

Inventor： Jeong Hun LEE

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C7/1084 ,  G11C7/1087

Abstract: A method for conducting reference voltage training includes setting levels of a reference voltage in response to code signals and receiving and storing data for the respective levels of the reference voltage, and simultaneously outputting the stored data.

Abstract translation: 用于进行参考电压训练的方法包括响应于代码信号设置参考电压的电平，并且接收和存储参考电压的各个电平的数据，并同时输出所存储的数据。

公开(公告)号：US20120081100A1

公开(公告)日：2012-04-05

申请号：US12983090

申请日：2010-12-31

Applicant: Jeong Hun LEE ,  Yong Mi KIM ,  Jeong Tae HWANG

Inventor： Jeong Hun LEE ,  Yong Mi KIM ,  Jeong Tae HWANG

IPC: G05F3/02

CPC classification number: G11C5/147 ,  G11C29/021

Abstract: A semiconductor apparatus includes a comparison voltage generation unit configured to generate a plurality of different comparison voltages, a reference voltage generation unit configured to receive a generation code from an external system, select one of the plurality of the different comparison voltages according to the generation code, and generate a reference voltage, and a reference voltage determination unit configured to receive the generation code and an expected reference voltage from the external system, check whether a level of the expected reference voltage is in a target range, and output a check result to the external system.

Abstract translation: 一种半导体装置，包括：被配置为生成多个不同的比较电压的比较电压生成单元，被配置为从外部系统接收生成代码的基准电压生成单元，根据生成代码选择所述多个不同的比较电压中的一个 并产生参考电压，参考电压确定单元被配置为从外部系统接收生成代码和预期参考电压，检查预期参考电压的电平是否在目标范围内，并将检查结果输出到 外部系统。

公开(公告)号：US20130107641A1

公开(公告)日：2013-05-02

申请号：US13339050

申请日：2011-12-28

Applicant: Jeong Hun LEE

Inventor： Jeong Hun LEE

IPC: G11C5/14 ,  G11C7/00

CPC classification number: G11C5/147 ,  G11C7/1045 ,  G11C7/1057 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2254

Abstract: A semiconductor system includes a controller configured to apply code signals for setting levels of a reference voltage and data, and to receive output data. The semiconductor system also includes a semiconductor device configured to receive the data for the respective levels of the reference voltage set according to the code signals, to compare the reference voltages with the data to generate new data, to store the new data as internal data, and to process the stored internal data to output as the output data.

Abstract translation: 半导体系统包括被配置为应用用于设置参考电压和数据的电平的代码信号并且接收输出数据的控制器。 半导体系统还包括：半导体器件，被配置为根据代码信号接收针对参考电压组的各个电平的数据，以将参考电压与数据进行比较以生成新数据，以将新数据存储为内部数据， 并处理存储的内部数据作为输出数据输出。

公开(公告)号：US20120008431A1

公开(公告)日：2012-01-12

申请号：US13033685

申请日：2011-02-24

Applicant: Jeong Hun LEE

Inventor： Jeong Hun LEE

IPC: G11C5/14 ,  G11C7/00 ,  H03K17/28 ,  H03K5/22 ,  H03K17/00

CPC classification number: G11C11/4072 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  H03K5/08 ,  H03M1/765

Abstract: An integrated circuit includes a reference voltage level setting circuit and a reference voltage generation circuit. The reference voltage level setting circuit is configured to set a level of an input reference voltage to a preset level in a power-up period or a self-refresh mode. The reference voltage generation circuit is configured to select one of a plurality of reference voltages and output the selected reference voltage as the input reference voltage when the power-up period is ended and an operation mode is not in the self-refresh mode.

Abstract translation: 集成电路包括参考电压电平设置电路和参考电压产生电路。 参考电压电平设置电路被配置为在上电周期或自刷新模式下将输入参考电压的电平设置为预设电平。 参考电压产生电路被配置为当上电周期结束并且操作模式不处于自刷新模式时，选择多个参考电压中的一个并输出所选择的参考电压作为输入参考电压。