利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

13 条记录 (耗时 0.03 秒)

    Chip lockout protection scheme for integrated circuit devices and insertion thereof
    3.
    发明授权
    Chip lockout protection scheme for integrated circuit devices and insertion thereof 失效
    集成电路器件的芯片锁定保护方案及其插入

    公开(公告)号：US08484481B2

    公开(公告)日：2013-07-09

    申请号：US12764144

    申请日：2010-04-21

    申请人： Jesse E. Craig ,  Stanley B. Stanski ,  Scott T. Vento

    发明人： Jesse E. Craig ,  Stanley B. Stanski ,  Scott T. Vento

    IPC分类号： G06F21/00

    CPC分类号： G06F21/31 ,  G06F2221/2127

    摘要： A system for implementing a chip lockout protection scheme for an IC device includes an on-chip password register that stores a password externally input by a user; an on-chip security block that generates a chip unlock signal, depending on whether the externally input password matches a correct password; an on-chip false data generator; an input protection scheme configured to gate the external data inputs to functional chip circuitry upon entry of the correct password; and an output protection scheme in communication configured to steer true chip data to external outputs of the IC device upon entry of the correct password, and to steer false data generated by the false data generator to the external outputs upon entry of an incorrect password. The false generated by the false data generator is deterministic and based upon external data inputs, thereby obfuscating whether or not the correct password has been entered.

    摘要翻译： 一种用于实现用于IC设备的芯片锁定保护方案的系统包括存储由用户外部输入的密码的片上密码寄存器; 片上安全块，根据外部输入的密码是否匹配正确的密码，产生芯片解锁信号; 片上虚拟数据发生器; 输入保护方案，被配置为在输入正确的密码时将外部数据输入门控到功能芯片电路; 以及通信中的输出保护方案，被配置为在输入正确的密码时将真实芯片数据引导到IC设备的外部输出，并且在输入不正确的密码时将由伪数据生成器产生的假数据转换到外部输出。 由假数据发生器产生的错误是确定性的，并且基于外部数据输入，从而混淆是否输入了正确的密码。

    Chip Lockout Protection Scheme for Integrated Circuit Devices and Insertion Thereof
    4.
    发明申请
    Chip Lockout Protection Scheme for Integrated Circuit Devices and Insertion Thereof 失效
    集成电路器件芯片锁定保护方案及其插入

    公开(公告)号：US20110016326A1

    公开(公告)日：2011-01-20

    申请号：US12764144

    申请日：2010-04-21

    申请人： Jesse E. Craig ,  Stanley B. Stanski ,  Scott T. Vento

    发明人： Jesse E. Craig ,  Stanley B. Stanski ,  Scott T. Vento

    IPC分类号： G06F21/00

    CPC分类号： G06F21/31 ,  G06F2221/2127

    摘要： A system for implementing a chip lockout protection scheme for an IC device includes an on-chip password register that stores a password externally input by a user; an on-chip security block that generates a chip unlock signal, depending on whether the externally input password matches a correct password; an on-chip false data generator; an input protection scheme configured to gate the external data inputs to functional chip circuitry upon entry of the correct password; and an output protection scheme in communication configured to steer true chip data to external outputs of the IC device upon entry of the correct password, and to steer false data generated by the false data generator to the external outputs upon entry of an incorrect password. The false generated by the false data generator is deterministic and based upon external data inputs, thereby obfuscating whether or not the correct password has been entered.

    摘要翻译： 一种用于实现用于IC设备的芯片锁定保护方案的系统包括存储由用户外部输入的密码的片上密码寄存器; 片上安全块，根据外部输入的密码是否匹配正确的密码，产生芯片解锁信号; 片上虚拟数据发生器; 输入保护方案，被配置为在输入正确的密码时将外部数据输入门控到功能芯片电路; 以及通信中的输出保护方案，被配置为在输入正确的密码时将真实芯片数据引导到IC设备的外部输出，并且在输入不正确的密码时将由伪数据生成器产生的假数据转换到外部输出。 由假数据发生器产生的错误是确定性的，并且基于外部数据输入，从而混淆是否输入了正确的密码。

    Design Structure for a Clock System for a Plurality of Functional Blocks
    6.
    发明申请
    Design Structure for a Clock System for a Plurality of Functional Blocks 审中-公开
    用于多个功能块的时钟系统的设计结构

    公开(公告)号：US20090172627A1

    公开(公告)日：2009-07-02

    申请号：US11966171

    申请日：2007-12-28

    申请人： Jesse E. Craig ,  Stanley B. Stanski ,  Scott T. Vento

    发明人： Jesse E. Craig ,  Stanley B. Stanski ,  Scott T. Vento

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： A design structure for a clock system for a plurality of functional blocks designed using a method of reducing peak power that utilizes connectivity and/or timing information among a plurality of design partitions of an integrated circuit system to create a clock system that reduces peak power consumption across the system. The method used to create the design structure includes sorting the design partitions according to a connectivity model, a timing model, or both, and assigning interleaved clock signals as a function of the design partition ordering. The clock system is created as a function of the interleaved clock signals.

    摘要翻译： 一种用于多个功能块的时钟系统的设计结构，其使用降低峰值功率的方法设计，所述方法利用集成电路系统的多个设计分区之间的连接性和/或定时信息来创建降低峰值功率消耗的时钟系统 跨系统。 用于创建设计结构的方法包括根据连接模型，时序模型或两者对设计分区进行排序，以及根据设计分区排序分配交织的时钟信号。 时钟系统是根据交错的时钟信号产生的。

    METHOD OF REDUCING PEAK POWER CONSUMPTION IN AN INTEGRATED CIRCUIT SYSTEM
    7.
    发明申请
    METHOD OF REDUCING PEAK POWER CONSUMPTION IN AN INTEGRATED CIRCUIT SYSTEM 审中-公开
    降低集成电路系统中峰值功耗的方法

    公开(公告)号：US20080270965A1

    公开(公告)日：2008-10-30

    申请号：US11739251

    申请日：2007-04-24

    申请人： Jesse E. Craig ,  Stanley B. Stanski ,  Scott T. Vento

    发明人： Jesse E. Craig ,  Stanley B. Stanski ,  Scott T. Vento

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/62 ,  G06F2217/78

    摘要： A method that utilizes connectivity and/or timing information among a plurality of design partitions of an circuit system to create a clock system that reduces peak power consumption across the system. The method includes sorting the design partitions according to a connectivity model, a timing model, or both, and assigning interleaved clock signals as a function of the design partition ordering. The clock system is created as a function of the interleaved clock signals.

    摘要翻译： 一种利用电路系统的多个设计分区中的连接和/或定时信息来创建可减少整个系统的峰值功率消耗的时钟系统的方法。 该方法包括根据连接模型，时序模型或两者来分类设计分区，以及根据设计分区排序分配交错时钟信号。 时钟系统是根据交错的时钟信号产生的。

    System and method for system-on-chip interconnect verification
    9.
    发明授权
    System and method for system-on-chip interconnect verification 失效
    系统级芯片互连验证的系统和方法

    公开(公告)号：US07313738B2

    公开(公告)日：2007-12-25

    申请号：US10906388

    申请日：2005-02-17

    申请人： Serafino Bueti ,  Adam Courchesne ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    发明人： Serafino Bueti ,  Adam Courchesne ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    IPC分类号： G01R31/28

    CPC分类号： G06F11/261 ,  G01R31/31717 ,  G01R31/318513 ,  G06F11/2236 ,  G06F17/5022

    摘要： A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

    摘要翻译： 一种用于验证片上系统互连的系统和方法包括：第一线性反馈移位寄存器，其耦合到第一片上系统分量的输出接口;第二线性反馈移位寄存器，其在第二片上系统组件 以及耦合到第二线性反馈移位寄存器和第二片上系统的输入接口的比较器。 另一种验证方法包括使用第一线性反馈移位寄存器和第二线性反馈移位寄存器使用相同的第一初始状态来产生伪随机数序列，并且将第一线性反馈移位寄存器的输出与第二线性反馈移位寄存器的输出进行比较 线性反馈移位寄存器和报告错误比较。

    System and method for system-on-chip interconnect verification
    10.
    发明授权
    System and method for system-on-chip interconnect verification 有权
    系统级芯片互连验证的系统和方法

    公开(公告)号：US07865789B2

    公开(公告)日：2011-01-04

    申请号：US11819748

    申请日：2007-06-28

    申请人： Serafino Bueti ,  Adam Courchesne ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    发明人： Serafino Bueti ,  Adam Courchesne ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    IPC分类号： G01R31/28

    CPC分类号： G06F11/261 ,  G01R31/31717 ,  G01R31/318513 ,  G06F11/2236 ,  G06F17/5022

    摘要： A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

    摘要翻译： 一种用于验证片上系统互连的系统和方法包括：第一线性反馈移位寄存器，其耦合到第一片上系统分量的输出接口;第二线性反馈移位寄存器，其在第二片上系统组件 以及耦合到第二线性反馈移位寄存器和第二片上系统的输入接口的比较器。 另一种验证方法包括使用第一线性反馈移位寄存器和第二线性反馈移位寄存器使用相同的第一初始状态来产生伪随机数序列，并且将第一线性反馈移位寄存器的输出与第二线性反馈移位寄存器的输出进行比较 线性反馈移位寄存器和报告错误比较。