公开(公告)号：US20090173994A1

公开(公告)日：2009-07-09

申请号：US12251054

申请日：2008-10-14

申请人： Ji-Young Min ,  Si-Hyung Lee ,  Heedon Hwang ,  Si-Young Choi ,  Sangbom Kang ,  Dongsoo Woo

发明人： Ji-Young Min ,  Si-Hyung Lee ,  Heedon Hwang ,  Si-Young Choi ,  Sangbom Kang ,  Dongsoo Woo

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66553 ,  H01L21/28079 ,  H01L21/28114 ,  H01L29/4236

摘要： A recess gate of a semiconductor device is provided, comprising: a substrate having a recess formed therein; a metal layer formed at the bottom of the recess; a polysilicon layer formed over the metal layer; and a source region and a drain region formed adjacent to the polysilicon layer and spaced from the metal layer. A method of forming a semiconductor device is also provided, comprising forming a substrate and a source and drain layer; forming a recess and depositing a gate insulation layer therein; forming a first conductive layer on the gate insulation layer; forming a first conductive layer pattern by recessing the first conductive layer; forming a second conductive layer on the first conductive layer pattern; forming a second conductive layer pattern by patterning the second conductive layer to overlap the source and drain layer; depositing an insulating layer on the second conductive layer pattern and the source and drain layer; and planarizing the insulating layer to form a cap on the second conductive layer pattern.

摘要翻译： 提供半导体器件的凹槽，其包括：形成有凹部的基板; 形成在所述凹部的底部的金属层; 形成在所述金属层上的多晶硅层; 以及与所述多晶硅层相邻形成并与所述金属层隔开形成的源极区域和漏极区域。 还提供了一种形成半导体器件的方法，包括形成衬底和源极和漏极层; 形成凹部并在其中沉积栅极绝缘层; 在所述栅绝缘层上形成第一导电层; 通过使所述第一导电层凹陷来形成第一导电层图案; 在所述第一导电层图案上形成第二导电层; 通过图案化所述第二导电层以与所述源极和漏极层重叠而形成第二导电层图案; 在第二导电层图案和源极和漏极层上沉积绝缘层; 并且平坦化绝缘层以在第二导电层图案上形成帽。

公开(公告)号：US08012828B2

公开(公告)日：2011-09-06

申请号：US12251054

申请日：2008-10-14

申请人： Ji-Young Min ,  Si-Hyung Lee ,  Heedon Hwang ,  Si-Young Choi ,  Sangbom Kang ,  Dongsoo Woo

发明人： Ji-Young Min ,  Si-Hyung Lee ,  Heedon Hwang ,  Si-Young Choi ,  Sangbom Kang ,  Dongsoo Woo

IPC分类号： H01L21/336

CPC分类号： H01L29/66553 ,  H01L21/28079 ,  H01L21/28114 ,  H01L29/4236

摘要： A recess gate of a semiconductor device is provided, comprising: a substrate having a recess formed therein; a metal layer formed at the bottom of the recess; a polysilicon layer formed over the metal layer; and a source region and a drain region formed adjacent to the polysilicon layer and spaced from the metal layer. A method of forming a semiconductor device is also provided, comprising forming a substrate and a source and drain layer; forming a recess and depositing a gate insulation layer therein; forming a first conductive layer on the gate insulation layer; forming a first conductive layer pattern by recessing the first conductive layer; forming a second conductive layer on the first conductive layer pattern; forming a second conductive layer pattern by patterning the second conductive layer to overlap the source and drain layer; depositing an insulating layer on the second conductive layer pattern and the source and drain layer; and planarizing the insulating layer to form a cap on the second conductive layer pattern.

摘要翻译： 提供半导体器件的凹槽，其包括：形成有凹部的基板; 形成在所述凹部的底部的金属层; 形成在所述金属层上的多晶硅层; 以及与所述多晶硅层相邻形成并与所述金属层隔开形成的源极区域和漏极区域。 还提供了一种形成半导体器件的方法，包括形成衬底和源极和漏极层; 形成凹部并在其中沉积栅极绝缘层; 在所述栅绝缘层上形成第一导电层; 通过使所述第一导电层凹陷来形成第一导电层图案; 在所述第一导电层图案上形成第二导电层; 通过图案化所述第二导电层以与所述源极和漏极层重叠而形成第二导电层图案; 在第二导电层图案和源极和漏极层上沉积绝缘层; 并且平坦化绝缘层以在第二导电层图案上形成帽。

公开(公告)号：US09443930B2

公开(公告)日：2016-09-13

申请号：US14834465

申请日：2015-08-25

申请人： Junsoo Kim ,  Dongjin Lee ,  Dongsoo Woo ,  Jun-Bum Lee ,  Sang-Il Han

发明人： Junsoo Kim ,  Dongjin Lee ,  Dongsoo Woo ,  Jun-Bum Lee ,  Sang-Il Han

IPC分类号： H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L27/088 ,  H01L27/108 ,  H01L27/22 ,  H01L27/24

CPC分类号： H01L29/0653 ,  H01L27/088 ,  H01L27/10805 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/228 ,  H01L27/2436 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： A semiconductor device may include a semiconductor substrate including an active region defined by a trench, a device isolation layer provided in the trench to surround the active region, a gate electrode extending in a direction crossing the active region, and formed on the active region and the device isolation layer, and a gate insulating layer between the active region and the gate electrode. The active region may have a first conductivity type, and the device isolation layer may include a first silicon oxide layer on an inner surface of the first trench and a different layer, selected from one of first metal oxide layer and a negatively-charged layer, on the first silicon oxide layer.

摘要翻译： 半导体器件可以包括半导体衬底，其包括由沟槽限定的有源区，设置在沟槽中以围绕有源区的器件隔离层，在与有源区交叉的方向上延伸并形成在有源区和 器件隔离层以及有源区和栅电极之间的栅极绝缘层。 有源区可以具有第一导电类型，并且器件隔离层可以包括在第一沟槽的内表面上的第一氧化硅层和选自第一金属氧化物层和带负电荷层之一的不同层， 在第一氧化硅层上。