公开(公告)号：US08241975B2

公开(公告)日：2012-08-14

申请号：US13198507

申请日：2011-08-04

申请人： Jiankang Bu ,  Lee James Jacobson ,  Andre Paul Labonte

发明人： Jiankang Bu ,  Lee James Jacobson ,  Andre Paul Labonte

IPC分类号： H01L21/8238

CPC分类号： H01L29/42332 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7887

摘要： A system and method is disclosed for providing a low voltage high density multi-bit storage flash memory. A dual bit memory cell of the invention comprises a substrate having a common source, a first drain and first channel, and a second drain and a second channel. A common control gate is located above the source. A first floating gate and a second floating gate are located on opposite sides of the control gate. Each floating gate is formed with a sharp tip adjacent to the control gate and an upper curved surface that follows a contour of the surface of the control gate. The sharp tips of the floating gates efficiently discharge electrons into the control gate when the memory cell is erased. The curved surfaces increase capacitor coupling between the control gate and the floating gates.

摘要翻译： 公开了一种用于提供低电压高密度多位存储闪存的系统和方法。 本发明的双位存储器单元包括具有公共源极，第一漏极和第一沟道以及第二漏极和第二沟道的衬底。 公共控制门位于源的上方。 第一浮栅和第二浮栅位于控制栅的相对侧。 每个浮动栅极形成有与控制栅极相邻的尖锐尖端以及跟随控制栅极表面轮廓的上部曲面。 当存储单元被擦除时，浮动栅极的尖端有效地将电子放电到控制栅极中。 曲面增加了控制栅极和浮栅之间的电容耦合。

公开(公告)号：US20110287596A1

公开(公告)日：2011-11-24

申请号：US13198507

申请日：2011-08-04

申请人： Jiankang Bu ,  Lee James Jacobson ,  Andre Paul Labonte

发明人： Jiankang Bu ,  Lee James Jacobson ,  Andre Paul Labonte

IPC分类号： H01L21/336

CPC分类号： H01L29/42332 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7887

摘要： A system and method is disclosed for providing a low voltage high density multi-bit storage flash memory. A dual bit memory cell of the invention comprises a substrate having a common source, a first drain and first channel, and a second drain and a second channel. A common control gate is located above the source. A first floating gate and a second floating gate are located on opposite sides of the control gate. Each floating gate is formed with a sharp tip adjacent to the control gate and an upper curved surface that follows a contour of the surface of the control gate. The sharp tips of the floating gates efficiently discharge electrons into the control gate when the memory cell is erased. The curved surfaces increase capacitor coupling between the control gate and the floating gates.

摘要翻译： 公开了一种用于提供低电压高密度多位存储闪存的系统和方法。 本发明的双位存储器单元包括具有公共源极，第一漏极和第一沟道以及第二漏极和第二沟道的衬底。 公共控制门位于源的上方。 第一浮栅和第二浮栅位于控制栅的相对侧。 每个浮动栅极形成有与控制栅极相邻的尖锐尖端以及跟随控制栅极表面轮廓的上部曲面。 当存储单元被擦除时，浮动栅极的尖端有效地将电子放电到控制栅极中。 曲面增加了控制栅极和浮栅之间的电容耦合。

公开(公告)号：US08004032B1

公开(公告)日：2011-08-23

申请号：US11437564

申请日：2006-05-19

申请人： Jiankang Bu ,  Lee James Jacobson ,  Andre Paul Labonte

发明人： Jiankang Bu ,  Lee James Jacobson ,  Andre Paul Labonte

IPC分类号： H01L29/788

CPC分类号： H01L29/42332 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7887

摘要： A system and method is disclosed for providing a low voltage high density multi-bit storage flash memory. A dual bit memory cell of the invention comprises a substrate having a common source, a first drain and first channel, and a second drain and a second channel. A common control gate is located above the source. A first floating gate and a second floating gate are located on opposite sides of the control gate. Each floating gate is formed with a sharp tip adjacent to the control gate and an upper curved surface that follows a contour of the surface of the control gate. The sharp tips of the floating gates efficiently discharge electrons into the control gate when the memory cell is erased. The curved surfaces increase capacitor coupling between the control gate and the floating gates.

摘要翻译： 公开了一种用于提供低电压高密度多位存储闪存的系统和方法。 本发明的双位存储器单元包括具有公共源极，第一漏极和第一沟道以及第二漏极和第二沟道的衬底。 公共控制门位于源的上方。 第一浮栅和第二浮栅位于控制栅的相对侧。 每个浮动栅极形成有与控制栅极相邻的尖锐尖端以及跟随控制栅极表面轮廓的上部曲面。 当存储单元被擦除时，浮动栅极的尖端有效地将电子放电到控制栅极中。 曲面增加了控制栅极和浮栅之间的电容耦合。

公开(公告)号：US08114738B2

公开(公告)日：2012-02-14

申请号：US12803073

申请日：2010-06-18

申请人： Jiankang Bu ,  David Courtney Parker

发明人： Jiankang Bu ,  David Courtney Parker

IPC分类号： H01L21/336

CPC分类号： H01L29/7881 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825

摘要： A system and method are disclosed for increasing the reliability of a channel erase procedure in an electrically erasable programmable read only memory (EEPROM) memory cell. A memory cell of the present invention comprises a program gate, a control gate, and a floating gate that erase data using a channel erase procedure. An erase capacitor is coupled to the floating gate to provide a low voltage bias that decreases the voltage that is required to perform a Fowler-Nordheim erase process in the memory cell. The erase capacitor of the present invention is formed without adding a step in the manufacturing process of the memory cell. Memory cells of the present invention are low cost, high endurance, low voltage memory cells.

摘要翻译： 公开了用于增加电可擦除可编程只读存储器（EEPROM）存储器单元中的通道擦除过程的可靠性的系统和方法。 本发明的存储单元包括使用信道擦除过程擦除数据的程序门，控制栅极和浮置栅极。 擦除电容器耦合到浮置栅极以提供降低在存储器单元中执行Fowler-Nordheim擦除处理所需的电压的低电压偏压。 本发明的擦除电容器在不增加存储单元的制造过程中的步骤的情况下形成。 本发明的存储单元是低成本，高耐久性，低电压存储单元。

公开(公告)号：US08097923B2

公开(公告)日：2012-01-17

申请号：US12803989

申请日：2010-07-12

申请人： Thanas Budri ,  Jiankang Bu

发明人： Thanas Budri ,  Jiankang Bu

IPC分类号： H01L27/088

CPC分类号： H01L21/823892 ,  H01L21/823857 ,  H01L27/11526 ,  H01L27/11546 ,  Y10S438/981

摘要： A non-volatile memory cell includes a program transistor and a control capacitor. A portion of a substrate associated with the program transistor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, and P-well implantations). Similarly, a portion of the substrate associated with the control capacitor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, P-well, and N-well implantations). These portions of the substrate may have faster oxidation rates than other portions of the substrate, allowing a thicker front-end gate oxide to be formed over these portions of the substrate. In addition, a rapid thermal process anneal can be performed, which may reduce defects in the front-end gate oxide and increase its quality without having much impact on the oxide over the other portions of the substrate.

摘要翻译： 非易失性存储单元包括程序晶体管和控制电容器。 与程序晶体管相关联的衬底的一部分暴露于多次注入（例如DNW，HiNWell，HiPWell和P阱注入）。 类似地，与控制电容器相关联的衬底的一部分暴露于多次注入（例如DNW，HiNWell，HiPWell，P阱和N阱注入）。 衬底的这些部分可以具有比衬底的其它部分更快的氧化速率，允许在衬底的这些部分上形成较厚的前端栅极氧化物。 此外，可以进行快速热处理退火，这可以减少前端栅极氧化物中的缺陷并提高其质量，而不会对衬底的其它部分上的氧化物产生太大影响。

公开(公告)号：US08198708B2

公开(公告)日：2012-06-12

申请号：US13040844

申请日：2011-03-04

申请人： Jiankang Bu ,  Henry G. Prosack, Jr. ,  David Courtney Parker ,  Heather McCulloh

发明人： Jiankang Bu ,  Henry G. Prosack, Jr. ,  David Courtney Parker ,  Heather McCulloh

IPC分类号： H01L23/58

CPC分类号： H01L29/7881 ,  H01L29/42324 ,  H01L29/513

摘要： A system and method is disclosed for improving complementary metal oxide semiconductor (CMOS) compatible non volatile memory (NVM) retention reliability in memory cells. A memory cell of the invention comprises a backend layer that reduces charge leakage from a floating gate of the memory cell. A first bottom portion of the backend layer is formed from a first layer of silicon oxynitride having a low value of defect/trap density. A second top portion of the backend layer is formed from a second layer of silicon oxynitride having a high value of defect/trap density. The first layer of silicon oxynitride inhibits electron transport and the second layer of silicon oxynitride protects CMOS devices from plasma induced damage.

摘要翻译： 公开了用于改善存储器单元中互补金属氧化物半导体（CMOS）兼容的非易失性存储器（NVM）保持可靠性的系统和方法。 本发明的存储器单元包括一个后端层，该后端层减少了来自存储单元的浮动栅极的电荷泄漏。 后端层的第一底部部分由具有低缺陷/陷阱密度值的第一氮氧化硅层形成。 后端层的第二顶部由具有高缺陷/陷阱密度值的第二氮氧化硅层形成。 第一层氮氧化硅抑制电子传输，第二层氮氧化硅保护CMOS器件免受等离子体引起的损伤。

公开(公告)号：US07855146B1

公开(公告)日：2010-12-21

申请号：US11901654

申请日：2007-09-18

申请人： Li-Heng Chou ,  Jiankang Bu

发明人： Li-Heng Chou ,  Jiankang Bu

IPC分类号： H01L21/47

CPC分类号： H01L21/32139 ,  G03F7/70283 ,  G03F7/70333 ,  G03F7/70466 ,  H01L21/0274 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/42376 ,  H01L29/6659

摘要： A method for forming a transistor gate includes performing a first exposure of a photo-resist material on a semiconductor device. The first exposure defines a line pattern in the photo-resist material. The method also includes performing a second exposure of the photo-resist material, where the second exposure trims a resist profile of the line pattern. The method further includes etching a conductive material on the semiconductor device to form a transistor gate based on the line pattern. The first exposure could represent a best focus exposure of the photo-resist material, and the second exposure could represent a positive focus exposure of the photo-resist material. The trimming of the line pattern's resist profile may cause the transistor gate to have at least one of a rounded edge and a rounded corner. This may allow a thicker insulating material, such as tetraethylorthosilicate, to be deposited around portions of the transistor gate.

摘要翻译： 一种用于形成晶体管栅极的方法包括在半导体器件上执行光致抗蚀剂材料的第一次曝光。 第一曝光定义了光刻胶材料中的线图案。 该方法还包括执行光刻胶材料的第二曝光，其中第二曝光修剪线图案的抗蚀剂轮廓。 该方法还包括在半导体器件上蚀刻导电材料，以形成基于线图案的晶体管栅极。 第一曝光可以代表光致抗蚀剂材料的最佳聚焦曝光，第二次曝光可以代表光致抗蚀材料的正焦点曝光。 线图案的抗蚀剂轮廓的修整可能导致晶体管栅极具有圆形边缘和圆角中的至少一个。 这可能允许在晶体管栅极的部分周围沉积较厚的绝缘材料，例如原硅酸四乙酯。

公开(公告)号：US07790491B1

公开(公告)日：2010-09-07

申请号：US12151437

申请日：2008-05-07

申请人： Li-Heng Chou ,  Jiankang Bu

发明人： Li-Heng Chou ,  Jiankang Bu

IPC分类号： H01L21/00

CPC分类号： H01L27/112 ,  H01L27/11206

摘要： A method includes forming a release layer of a semiconductor device being fabricated, where the release layer has a trapezoidal shape. The method also includes forming a cantilever, which has a cantilever arm formed over the release layer. The method further includes removing at least part of the release layer from under the cantilever arm. The release layer could be formed using a photo-resist material. The photo-resist material can be patterned by exposing the photo-resist material using multiple exposures. A first exposure could expose a portion of the photo-resist material, where the exposed portion has substantially vertical sides. A second exposure could give the exposed portion of the photo-resist material slanted sides. A wet etch could be performed to remove the release layer from under the cantilever arm.

摘要翻译： 一种方法包括形成半导体器件的剥离层，其中剥离层具有梯形形状。 该方法还包括形成悬臂，其具有形成在释放层上的悬臂。 该方法还包括从悬臂下面移除至少部分释放层。 剥离层可以使用光致抗蚀材料形成。 可以通过使用多次曝光曝光光致抗蚀材料来对光致抗蚀剂材料进行图案化。 第一次曝光可以暴露一部分光刻胶材料，其中暴露部分具有基本垂直的侧面。 第二次曝光可能会使光刻胶材料的露出部分倾斜。 可以进行湿蚀刻以从悬臂下面移除释放层。

公开(公告)号：US07781289B1

公开(公告)日：2010-08-24

申请号：US11799921

申请日：2007-05-03

申请人： Thanas Budri ,  Jiankang Bu

发明人： Thanas Budri ,  Jiankang Bu

IPC分类号： H01L21/8234

CPC分类号： H01L21/823892 ,  H01L21/823857 ,  H01L27/11526 ,  H01L27/11546 ,  Y10S438/981

摘要： A non-volatile memory cell includes a program transistor and a control capacitor. A portion of a substrate associated with the program transistor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, and P-well implantations). Similarly, a portion of the substrate associated with the control capacitor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, P-well, and N-well implantations). These portions of the substrate may have faster oxidation rates than other portions of the substrate, allowing a thicker front-end gate oxide to be formed over these portions of the substrate. In addition, a rapid thermal process anneal can be performed, which may reduce defects in the front-end gate oxide and increase its quality without having much impact on the oxide over the other portions of the substrate.

摘要翻译： 非易失性存储单元包括程序晶体管和控制电容器。 与程序晶体管相关联的衬底的一部分暴露于多次注入（例如DNW，HiNWell，HiPWell和P阱注入）。 类似地，与控制电容器相关联的衬底的一部分暴露于多次注入（例如DNW，HiNWell，HiPWell，P阱和N阱注入）。 衬底的这些部分可以具有比衬底的其它部分更快的氧化速率，允许在衬底的这些部分上形成较厚的前端栅极氧化物。 此外，可以进行快速热处理退火，这可以减少前端栅极氧化物中的缺陷并提高其质量，而不会对衬底的其它部分上的氧化物产生太大影响。

公开(公告)号：US07646638B1

公开(公告)日：2010-01-12

申请号：US11899462

申请日：2007-09-06

申请人： Jiankang Bu

发明人： Jiankang Bu

IPC分类号： G11C11/34

CPC分类号： G11C16/0416 ,  G11C16/14 ,  G11C16/3468 ,  G11C2216/10 ,  H01L27/11521 ,  H01L27/11558

摘要： A memory cell includes a first transistor and a second transistor. The first transistor is configured as an erase capacitor, and the second transistor is configured as a program transistor. Gates of the first and second transistors are coupled together to form a floating gate. During an erase operation, a first voltage (like 12V-24V) is applied to the first transistor, such as to a source, a body, and a drain of the first transistor. A second voltage (like ground) is applied to the second transistor, such as to a source and a body of the second transistor. A drain of the second transistor could be grounded. The first and second voltages cause electron discharge from the floating gate through the first transistor and electron injection through the second transistor onto the floating gate. This helps to prevent an over-erase condition from forming in the memory cell.

摘要翻译： 存储单元包括第一晶体管和第二晶体管。 第一晶体管被配置为擦除电容器，并且第二晶体管被配置为编程晶体管。 第一和第二晶体管的栅极耦合在一起以形成浮置栅极。 在擦除操作期间，第一电压（例如12V-24V）被施加到第一晶体管，诸如第一晶体管的源极，主体和漏极。 第二电压（如接地）施加到第二晶体管，例如施加到第二晶体管的源极和主体。 第二晶体管的漏极可以接地。 第一和第二电压引起来自浮置栅极的电子从第一晶体管的放电和通过第二晶体管的电子注入浮置栅极。 这有助于防止在存储器单元中形成过度擦除条件。