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1.发明授权Capacity and density enhancement circuit for sub-threshold memory unit array 有权用于子阈值存储单元阵列的容量和密度增强电路公开(公告)号：US08345468B2
公开(公告)日：2013-01-01
申请号：US13322114
申请日：2009-08-18
IPC分类号： G11C11/24
CPC分类号： G11C11/412 , G11C7/12
摘要： A capacity and density enhancement circuit for a sub-threshold memory unit array which can decrease the drain current in the bit lines and enhance the pull-up capability of memory cells. The capacity and density enhancement circuit is composed of a first enhancement transistor, a second enhancement transistor, a first mask transmission gate, a second mask transmission gate, a first logic memory capacitor and a second logic memory capacitor.
摘要翻译： 一种用于子阈值存储单元阵列的容量和密度增强电路，其可以减小位线中的漏极电流并增强存储器单元的上拉能力。 容量和密度增强电路由第一增强晶体管，第二增强晶体管，第一掩模传输栅极，第二掩模传输栅极，第一逻辑存储电容器和第二逻辑存储电容器组成。
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2.发明申请公开(公告)号：US20120069635A1
公开(公告)日：2012-03-22
申请号：US13322114
申请日：2009-08-18
IPC分类号： G11C11/24
CPC分类号： G11C11/412 , G11C7/12
摘要： A capacity and density enhancement circuit for a sub-threshold memory unit array which can decrease the drain current in the bit lines and enhance the pull-up capability of memory cells. The capacity and density enhancement circuit is composed of a first enhancement transistor, a second enhancement transistor, a first mask transmission gate, a second mask transmission gate, a first logic memory capacitor and a second logic memory capacitor.
摘要翻译： 一种用于子阈值存储单元阵列的容量和密度增强电路，其可以减小位线中的漏极电流并增强存储器单元的上拉能力。 容量和密度增强电路由第一增强晶体管，第二增强晶体管，第一掩模传输栅极，第二掩模传输栅极，第一逻辑存储电容器和第二逻辑存储电容器组成。
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