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公开(公告)号：US08981527B2
公开(公告)日：2015-03-17
申请号：US13215237
申请日：2011-08-23
申请人： Jie-Ning Yang , Shih-Chieh Hsu , Yao-Chang Wang , Chi-Horn Pai , Chi-Sheng Tseng , Kun-Szu Tseng , Ying-Hung Chou , Chiu-Hsien Yeh
发明人： Jie-Ning Yang , Shih-Chieh Hsu , Yao-Chang Wang , Chi-Horn Pai , Chi-Sheng Tseng , Kun-Szu Tseng , Ying-Hung Chou , Chiu-Hsien Yeh
IPC分类号： H01L21/8234 , H01L49/02 , H01L27/06
CPC分类号： H01L28/20 , H01L27/0629
摘要： A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor.
摘要翻译： 一种用于形成与具有金属栅极的晶体管集成的电阻器的方法包括提供具有限定在其上的晶体管区域和电阻器区域的衬底，在晶体管区域中形成具有多晶硅虚拟栅极的晶体管，以及多晶硅主体部分，其中两个掺杂区域 在电阻器区域的两个相对端处，执行蚀刻工艺以去除多晶硅虚拟栅极以形成第一沟槽并去除掺杂区域的部分以形成两个第二沟槽，并且在第一沟槽中形成金属栅极以形成晶体管 在第二沟槽中分别具有金属栅极和金属结构以形成电阻器。
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公开(公告)号：US20130049168A1
公开(公告)日：2013-02-28
申请号：US13215237
申请日：2011-08-23
申请人： Jie-Ning Yang , Shih-Chieh Hsu , Yao-Chang Wang , Chi-Horn Pai , Chi-Sheng Tseng , Kun-Szu Tseng , Ying-Hung Chou , Chiu-Hsien Yeh
发明人： Jie-Ning Yang , Shih-Chieh Hsu , Yao-Chang Wang , Chi-Horn Pai , Chi-Sheng Tseng , Kun-Szu Tseng , Ying-Hung Chou , Chiu-Hsien Yeh
IPC分类号： H01L21/8234 , H01L27/06
CPC分类号： H01L28/20 , H01L27/0629
摘要： A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor.
摘要翻译： 一种用于形成与具有金属栅极的晶体管集成的电阻器的方法包括提供具有限定在其上的晶体管区域和电阻器区域的衬底，在晶体管区域中形成具有多晶硅虚拟栅极的晶体管，以及多晶硅主体部分，其中两个掺杂区域 在电阻器区域的两个相对端处，执行蚀刻工艺以去除多晶硅虚拟栅极以形成第一沟槽并去除掺杂区域的部分以形成两个第二沟槽，并且在第一沟槽中形成金属栅极以形成晶体管 在第二沟槽中分别具有金属栅极和金属结构以形成电阻器。
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公开(公告)号：US20110073957A1
公开(公告)日：2011-03-31
申请号：US12566678
申请日：2009-09-25
申请人： Kai-Ling Chiu , Victor-Chiang Liang , Chih-Yu Tseng , Kun-Szu Tseng , Cheng-Wen Fan , Hsin-Kai Chiang , Chih-Chen Hsueh
发明人： Kai-Ling Chiu , Victor-Chiang Liang , Chih-Yu Tseng , Kun-Szu Tseng , Cheng-Wen Fan , Hsin-Kai Chiang , Chih-Chen Hsueh
CPC分类号： H01L27/0629 , H01L28/20 , H01L28/24
摘要： A resistor is disclosed. The resistor is disposed on a substrate, in which the resistor includes: a dielectric layer disposed on the substrate; a polysilicon structure disposed on the dielectric layer; two primary resistance structures disposed on the dielectric layer and at two ends of the polysilicon structure; and a plurality of secondary resistance structures disposed on the dielectric layer and interlaced with the polysilicon structures.
摘要翻译： 公开了一种电阻器。 电阻器设置在基板上，其中电阻器包括：布置在基板上的电介质层; 设置在电介质层上的多晶硅结构; 布置在电介质层上并在多晶硅结构两端的两个初级电阻结构; 以及设置在电介质层上并与多晶硅结构隔行的多个次级电阻结构。
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公开(公告)号：US08252657B2
公开(公告)日：2012-08-28
申请号：US13072766
申请日：2011-03-27
IPC分类号： H01L21/20 , H01L21/8234 , H01L21/8244 , H01L21/8238 , H01L21/8222
CPC分类号： H01L27/0629 , H01L21/84 , H01L28/20
摘要： A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.
摘要翻译： 公开了一种用于制造金属栅极晶体管和电阻器的方法。 该方法包括以下步骤：提供具有晶体管区域和电阻器区域的衬底; 在电阻器区域的衬底中形成浅沟槽隔离; 在电阻区域的浅沟槽隔离中形成一个槽; 在所述晶体管区域中形成至少一个栅极和在所述电阻器区域的所述槽中形成电阻器; 并将栅极变换为金属栅极晶体管。
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公开(公告)号：US20120214284A1
公开(公告)日：2012-08-23
申请号：US13461791
申请日：2012-05-02
IPC分类号： H01L21/8234
CPC分类号： H01L27/0629 , H01L28/20 , H01L29/495 , H01L29/4966 , H01L29/66545
摘要： An integrated method includes fabricating a metal gate transistor and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a high resistance structure of the polysilicon resistor. When the dummy gate of the transistor is etched, the part of the high resistance structure is protected by the patterned photoresistor layer. The polysilicon resistor is formed simultaneously with the transistor. Furthermore, the polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.
摘要翻译： 集成方法包括制造金属栅极晶体管和多晶硅电阻器结构。 光电晶体层由SAB光掩模限定，并覆盖多晶硅电阻器的高电阻结构的一部分。 当蚀刻晶体管的虚拟栅极时，高电阻结构的部分被图案化的光敏电阻层保护。 多晶硅电阻器与晶体管同时形成。 此外，多晶硅电阻器仍然具有足够的电阻并且包括用于电连接的两个金属结构。
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公开(公告)号：US20110171810A1
公开(公告)日：2011-07-14
申请号：US13072766
申请日：2011-03-27
IPC分类号： H01L21/02
CPC分类号： H01L27/0629 , H01L21/84 , H01L28/20
摘要： A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.
摘要翻译： 公开了一种用于制造金属栅极晶体管和电阻器的方法。 该方法包括以下步骤：提供具有晶体管区域和电阻器区域的衬底; 在电阻器区域的衬底中形成浅沟槽隔离; 在电阻区域的浅沟槽隔离中形成一个槽; 在所述晶体管区域中形成至少一个栅极和在所述电阻器区域的所述槽中形成电阻器; 并将栅极变换为金属栅极晶体管。
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公开(公告)号：US08637936B2
公开(公告)日：2014-01-28
申请号：US12566678
申请日：2009-09-25
申请人： Kai-Ling Chiu , Victor-Chiang Liang , Chih-Yu Tseng , Kun-Szu Tseng , Cheng-Wen Fan , Hsin-Kai Chiang , Chih-Chen Hsueh
发明人： Kai-Ling Chiu , Victor-Chiang Liang , Chih-Yu Tseng , Kun-Szu Tseng , Cheng-Wen Fan , Hsin-Kai Chiang , Chih-Chen Hsueh
IPC分类号： H01L27/11
CPC分类号： H01L27/0629 , H01L28/20 , H01L28/24
摘要： A resistor is disclosed. The resistor is disposed on a substrate, in which the resistor includes: a dielectric layer disposed on the substrate; a polysilicon structure disposed on the dielectric layer; two primary resistance structures disposed on the dielectric layer and at two ends of the polysilicon structure; and a plurality of secondary resistance structures disposed on the dielectric layer and interlaced with the polysilicon structures.
摘要翻译： 公开了一种电阻器。 电阻器设置在基板上，其中电阻器包括：布置在基板上的电介质层; 设置在电介质层上的多晶硅结构; 布置在电介质层上并在多晶硅结构两端的两个初级电阻结构; 以及设置在电介质层上并与多晶硅结构隔行的多个次级电阻结构。
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8.发明申请METHOD FOR FABRICATING METAL GATE AND POLYSILICON RESISTOR AND RELATED POLYSILICON RESISTOR STRUCTURE 有权制造金属栅和多晶硅电阻的方法及相关多晶硅电阻结构公开(公告)号：US20100328022A1
公开(公告)日：2010-12-30
申请号：US12490334
申请日：2009-06-24
IPC分类号： H01C1/012 , H01L21/336 , H01L21/02
CPC分类号： H01L27/0629 , H01L28/20 , H01L29/495 , H01L29/4966 , H01L29/66545
摘要： An integrated method includes fabricating a metal gate and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a polysilicon structure of the polysilicon resistor. When the gate conductor of a poly gate transistor is etched, the part of the polysilicon structure is protected by the patterned photoresistor layer. After the polysilicon resistor and the metal gate are formed. The polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.
摘要翻译： 集成方法包括制造金属栅极和多晶硅电阻器结构。 光电晶体层由SAB光掩模限定并且覆盖多晶硅电阻器的多晶硅结构的一部分。 当蚀刻多晶硅晶体管的栅极导体时，多晶硅结构的一部分被图案化的光敏电阻层保护。 在形成多晶硅电阻器和金属栅极之后。 多晶硅电阻器仍然具有足够的电阻并且包括用于电连接的两个金属结构。
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9.发明授权Method for fabricating metal gate and polysilicon resistor and related polysilicon resistor structure 有权制造金属栅极和多晶硅电阻器及相关多晶硅电阻器结构的方法公开(公告)号：US08193900B2
公开(公告)日：2012-06-05
申请号：US12490334
申请日：2009-06-24
IPC分类号： H01C1/012
CPC分类号： H01L27/0629 , H01L28/20 , H01L29/495 , H01L29/4966 , H01L29/66545
摘要： An integrated method includes fabricating a metal gate and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a polysilicon structure of the polysilicon resistor. When the gate conductor of a poly gate transistor is etched, the part of the polysilicon structure is protected by the patterned photoresistor layer. After the polysilicon resistor and the metal gate are formed. The polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.
摘要翻译： 集成方法包括制造金属栅极和多晶硅电阻器结构。 光电晶体层由SAB光掩模限定并且覆盖多晶硅电阻器的多晶硅结构的一部分。 当蚀刻多晶硅晶体管的栅极导体时，多晶硅结构的一部分被图案化的光敏电阻层保护。 在形成多晶硅电阻器和金属栅极之后。 多晶硅电阻器仍然具有足够的电阻并且包括用于电连接的两个金属结构。
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公开(公告)号：US20110156161A1
公开(公告)日：2011-06-30
申请号：US12648873
申请日：2009-12-29
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0629 , H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including a substrate, a first device, a second device and an interlayer dielectric layer is provided. The substrate has a first area and a second area. The first device is disposed in the first area of the substrate and includes a first dielectric layer on the substrate and a metal gate on the first dielectric layer. The second device is in the second area of the substrate and includes a second dielectric layer on the substrate and, a polysilicon layer on the second dielectric layer. It is noted that the height of the polysilicon layer is less than that of the metal gate of the first device. The interlayer dielectric layer covers the second device.
摘要翻译： 提供了包括衬底，第一器件，第二器件和层间介电层的半导体器件。 衬底具有第一区域和第二区域。 第一器件设置在衬底的第一区域中，并且包括在衬底上的第一介电层和第一介电层上的金属栅极。 第二器件位于衬底的第二区域中，并且在衬底上包括第二电介质层，以及在第二介电层上的多晶硅层。 注意，多晶硅层的高度小于第一器件的金属栅极的高度。 层间绝缘层覆盖第二器件。
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