公开(公告)号：US20080210974A1

公开(公告)日：2008-09-04

申请号：US11972908

申请日：2008-01-11

申请人： Jifa Hao ,  John L. Benjamin ,  Randall L. Case ,  Joe L. Yun

发明人： Jifa Hao ,  John L. Benjamin ,  Randall L. Case ,  Joe L. Yun

IPC分类号： H01L29/739 ,  H01L29/78

CPC分类号： H01L29/0615 ,  H01L29/7395 ,  H01L29/8611

摘要： A power semiconductor device having high avalanche capability comprises an N+ doped substrate and, in sequence, N− doped, P− doped, and P+ doped semiconductor layers, the P− and P+ doped layers having a combined thickness of about 5 μm to about 12 μm. Recombination centers comprising noble metal impurities are disposed substantially in the N− and P− doped layers. A process for forming a power semiconductor device with high avalanche capability comprises: forming an N− doped epitaxial layer on an N+ doped substrate, forming a P− doped layer in the N− doped epitaxial layer, forming a P+ doped layer in the P− doped layer, and forming in the P− and N− doped layers recombination centers comprising noble metal impurities. The P+ and P−doped layers have a combined thickness of about 5 μm to about 12 μm.

摘要翻译： 具有高雪崩能力的功率半导体器件包括掺杂N +的衬底，并且依次掺杂N掺杂的P掺杂的P和 掺杂半导体层的掺杂P +和/或P +掺杂层具有约5μm至约12μm的组合厚度。 包含贵金属杂质的复合中心基本上设置在N +和P + - SUP掺杂层中。 用于形成具有高雪崩能力的功率半导体器件的工艺包括：在掺杂N +的衬底上形成掺杂N +的外延层，形成P + / SUP>掺杂层，在掺杂P的掺杂层中形成掺杂P +的掺杂层，并形成 包含贵金属杂质的掺杂层和复合掺杂层复合中心。 掺杂P +的掺杂层具有约5μm至约12μm的组合厚度。

公开(公告)号：US07332750B1

公开(公告)日：2008-02-19

申请号：US09654845

申请日：2000-09-01

申请人： Jifa Hao ,  John L. Benjamin ,  Randall L. Case ,  Jae J. Yun

发明人： Jifa Hao ,  John L. Benjamin ,  Randall L. Case ,  Jae J. Yun

IPC分类号： H01L29/74 ,  H01L29/30

CPC分类号： H01L29/0615 ,  H01L29/7395 ,  H01L29/8611

摘要： A power semiconductor device having high avalanche capability comprises an N+ doped substrate and, in sequence, N− doped, P− doped, and P+ doped semiconductor layers, the P− and P+ doped layers having a combined thickness of about 5 μm to about 12 μm. Recombination centers comprising noble metal impurities are disposed substantially in the N− and P− doped layers. A process for forming a power semiconductor device with high avalanche capability comprises: forming an N− doped epitaxial layer on an N+ doped substrate, forming a P− doped layer in the N− doped epitaxial layer, forming a P+ doped layer in the P− doped layer, and forming in the P− and N− doped layers recombination centers comprising noble metal impurities. The P+ and P− doped layers have a combined thickness of about 5 μm to about 12 μm.

摘要翻译： 具有高雪崩能力的功率半导体器件包括掺杂N +的衬底，并且依次掺杂N掺杂的P掺杂的P和 掺杂半导体层的掺杂P +和/或P +掺杂层具有约5μm至约12μm的组合厚度。 包含贵金属杂质的复合中心基本上设置在N +和P + - SUP掺杂层中。 用于形成具有高雪崩能力的功率半导体器件的工艺包括：在掺杂N +的衬底上形成掺杂N +的外延层，形成P + / SUP>掺杂层，在掺杂P的掺杂层中形成掺杂P +的掺杂层，并形成 包含贵金属杂质的掺杂层和复合掺杂层复合中心。 掺杂P +的掺杂层具有约5μm至约12μm的组合厚度。

公开(公告)号：US06358825B1

公开(公告)日：2002-03-19

申请号：US09718219

申请日：2000-11-21

申请人： Jifa Hao ,  Randall L. Case ,  John L. Benjamin

发明人： Jifa Hao ,  Randall L. Case ,  John L. Benjamin

IPC分类号： H01L2122

CPC分类号： H01L29/66128 ,  H01L29/868

摘要： In an improved process for controlling and improving minority carrier lifetime in a P-i-N diode, platinum is deposited on a surface of a silicon semiconductor substrate containing at least one PN junction. The substrate is heated to a temperature of about 800° C., and the platinum is diffused into the substrate as its temperature is increased at a rate of about 5° C./minute to a first selected temperature of about 850-950° C. Platinum diffusion is continued while the substrate is maintained at the first selected temperature for about 30-60 minutes. The substrate temperature is then increased at a rate of about 5° C./minute to a second selected temperature above 950° C. to about 1000° C., and the substrate is maintained at the second selected temperature for about 5-30 minutes before cooling.

摘要翻译： 在用于控制和改善P-i-N二极管中的少数载流子寿命的改进方法中，铂沉积在含有至少一个PN结的硅半导体衬底的表面上。 将基底加热到约800℃的温度，并且当铂以约5℃/分钟的速度升高至约850-950℃的第一选定温度时，铂扩散到基底中 铂基体继续扩散，同时将基底保持在第一选定温度约30-60分钟。 然后将衬底温度以约5℃/分钟的速率增加至高于950℃至约1000℃的第二选定温度，并将衬底保持在第二选定温度约5-30分钟 在冷却之前。