公开(公告)号：US07102382B2

公开(公告)日：2006-09-05

申请号：US10503427

申请日：2003-01-29

申请人： Joannes Christianus Drenth ,  Daniel Thommen ,  Zeljko Mrcarica ,  Kurt Henggeler

发明人： Joannes Christianus Drenth ,  Daniel Thommen ,  Zeljko Mrcarica ,  Kurt Henggeler

IPC分类号： G06F7/38 ,  H03K19/173 ,  H03K19/096

CPC分类号： H03K19/0016

摘要： The digital electronic circuit (1) includes a logic cell (2) for processing data (82) , a flip-flop (3) for storing data (83) processed in the logic cell (2), a power supply (4), and a clock (5) for triggering the flip-flop (3) . The logic cell (2) is disconnected from the power supply (4) when the clock (5) is not active, as it is not needed for memorizing of the flip-flop states, and connected with the power supply (4) when the clock (5) is enabled. For switching the power supply, a switch (7) switched by the clock enable (6) is arranged between the logic cell (2) and the power supply (4). Such a simple additional switch (7) occupies only a relatively small area on the chip, but permits a drastic reduction by about 90% of the leakage currents. The circuit (1) is especially design and may be used for instance in mobile telecommunication devices.

摘要翻译： 数字电子电路（1）包括用于处理数据（82）的逻辑单元（2），用于存储在逻辑单元（2）中处理的数据（83）的触发器（3），电源（4） 以及用于触发触发器（3）的时钟（5）。 当时钟（5）不活动时，逻辑单元（2）与电源（4）断开，因为不需要记忆触发器状态，并且当电源（4）与 时钟（5）被使能。 为了切换电源，在逻辑单元（2）和电源（4）之间布置由时钟使能（6）切换的开关（7）。 这种简单的附加开关（7）在芯片上仅占据相对小的面积，但允许大约90％的漏电流减少。 电路（1）是特别设计的，并且可以用于例如移动电信设备中。

公开(公告)号：US06636096B2

公开(公告)日：2003-10-21

申请号：US09969715

申请日：2001-10-03

申请人： Bernhard Schaffer ,  Daniel Thommen ,  Joannes Christianus Drenth

发明人： Bernhard Schaffer ,  Daniel Thommen ,  Joannes Christianus Drenth

IPC分类号： G06F104

CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C8/18

摘要： An integrated circuit has a clock input for receiving a primary clock signal, clock reconfiguring device fed by the clock input for generating one or more secondary reconfigured clock signals, and utility circuitry fed by the clock reconfiguring device for constituting application utility functions under synchronization by the secondary clock signals. In particular, the clock input a clock upscaling device for from the primary clock signal generating an intermediate clock signal with an upscaled frequency for thereby feeding the clock reconfiguring device. Furthermore, the clock reconfiguring device a has late-programmable and low power memory driven by the intermediate clock signal for generating the secondary reconfigured clock signals. These are wave-shape patterns read-out from a plurality of separately and sequentially drivable memory locations.