Fast initial acquisition & search device for a spread spectrum communication system
    2.
    发明申请
    Fast initial acquisition & search device for a spread spectrum communication system 审中-公开
    用于扩频通信系统的快速初始采集和搜索设备

    公开(公告)号:US20060245480A1

    公开(公告)日:2006-11-02

    申请号:US11373844

    申请日:2006-03-10

    申请人: Joel Medlock Uma Jha

    发明人: Joel Medlock Uma Jha

    IPC分类号: H04B1/707

    摘要: A fast initial acquisition and search device for a spread spectrum communication system is disclosed herein. The search device includes a memory for storing the first code sequence, and a plurality of computation circuits coupled in parallel to the memory. The search device also includes a plurality of threshold detector circuits. Each of the plurality of threshold detector circuits is respectively coupled to one of the plurality of computation circuits. Each of the plurality of computation circuits implements a unique phase offset for a second code sequence with respect to the first code sequence. A correlation operation is performed in parallel at each of the plurality of computation circuits followed by a threshold evaluation that indicates whether the correlation result satisfied a threshold value.

    摘要翻译: 本文公开了一种用于扩展频谱通信系统的快速初始采集和搜索装置。 搜索装置包括用于存储第一代码序列的存储器和并联耦合到存储器的多个计算电路。 搜索装置还包括多个阈值检测器电路。 多个阈值检测器电路中的每一个分别耦合到多个计算电路中的一个。 多个计算电路中的每一个相对于第一代码序列实现针对第二代码序列的唯一的相位偏移。 在多个计算电路中的每一个并行执行相关操作,接着是指示相关结果是否满足阈值的阈值评估。

    Method and apparatus to support multi standard, multi service base-stations for wireless voice and data netwoks
    3.
    发明申请
    Method and apparatus to support multi standard, multi service base-stations for wireless voice and data netwoks 审中-公开
    支持无线语音和数据网络的多标准多业务基站的方法和装置

    公开(公告)号:US20060039317A1

    公开(公告)日:2006-02-23

    申请号:US11200854

    申请日:2005-08-09

    IPC分类号: H04Q7/00

    摘要: An apparatus for digitally processing signals within wireless communications base-stations which includes a channel pooling signal processor and a digital signal processor. The channel pooling signal processor includes a plurality of computation units typically realized in a heterogeneous multiprocessing architecture, a test interface for testing the function of the plurality of the computation units, a general-purpose microprocessor for managing the dataflow into and out of the channel pooling signal processor as well as effecting the control and configuration of the computation units, and an interconnect mechanism for connecting the plurality of computation units to the input, output, test interface, and the general-purpose microprocessor.

    摘要翻译: 一种用于数字处理无线通信基站内的信号的装置,包括信道汇集信号处理器和数字信号处理器。 信道池信号处理器包括通常在异构多处理架构中实现的多个计算单元,用于测试多个计算单元的功能的测试接口,用于管理数据流进出信道池的通用微处理器 信号处理器以及实现计算单元的控制和配置,以及用于将多个计算单元连接到输入,输出,测试接口和通用微处理器的互连机构。

    Wireless spread spectrum communication platform using dynamically reconfigurable logic

    公开(公告)号:US20060003757A1

    公开(公告)日:2006-01-05

    申请号:US11193851

    申请日:2005-07-29

    IPC分类号: H04Q7/20

    摘要: A wireless spread spectrum communication platform for processing a communication signal is disclosed herein. The wireless communication platform includes a first computing element, a second computing element, and a reconfigurable interconnect. The first computing element is coupled to the second computing element via the reconfigurable interconnect. A design configuration of the first computing element is heterogeneous with respect to a design configuration of the second computing element. The reconfigurable interconnect has an uncommitted architecture, thereby allowing it to be configured by an outside source to couple portions of the first reconfigurable interconnect with portions of the second reconfigurable interconnect in a variety of combinations. The first computing element, the second computing element, and the reconfigurable interconnect operable to perform discrete functions suitable for processing of the communication signal.

    Wireless spread spectrum communication platform using dynamically reconfigurable logic
    5.
    发明申请
    Wireless spread spectrum communication platform using dynamically reconfigurable logic 有权
    无线扩频通信平台采用动态可重构逻辑

    公开(公告)号:US20050282534A1

    公开(公告)日:2005-12-22

    申请号:US11198692

    申请日:2005-08-05

    IPC分类号: H04B1/707 H04M3/00

    摘要: A wireless spread spectrum communication platform for processing a communication signal is disclosed herein. The wireless communication platform includes a first computing element, a second computing element, and a reconfigurable interconnect. The first computing element is coupled to the second computing element via the reconfigurable interconnect. A design configuration of the first computing element is heterogeneous with respect to a design configuration of the second computing element. The reconfigurable interconnect has an uncommitted architecture, thereby allowing it to be configured by an outside source to couple portions of the first reconfigurable interconnect with portions of the second reconfigurable interconnect in a variety of combinations. The first computing element, the second computing element, and the reconfigurable interconnect operable to perform discrete functions suitable for processing of the communication signal.

    摘要翻译: 本文公开了一种用于处理通信信号的无线扩频通信平台。 无线通信平台包括第一计算元件,第二计算元件和可重构互连。 第一计算元件经由可重构互连耦合到第二计算元件。 关于第二计算元件的设计配置,第一计算元件的设计配置是异构的。 可重配置互连具有未提交的架构,从而允许其由外部源配置以将第一可重配置互连的部分以各种组合耦合第二可重配置互连的部分。 第一计算元件,第二计算元件和可重构互连可操作以执行适于处理通信信号的离散功能。

    Apparatus and methods for sample selection and reuse of rake fingers in spread spectrum systems

    公开(公告)号:US20060291542A1

    公开(公告)日:2006-12-28

    申请号:US11447228

    申请日:2006-06-05

    IPC分类号: H04B1/00

    CPC分类号: H04B1/7117 H04B2201/70707

    摘要: An apparatus for reducing storage requirements and for allowing reuse of multiple rake fingers in a spread spectrum system includes a decimation circuit having an associated decimation factor, a memory coupled to the decimation circuit, and an interpolation circuit having an interpolation factor coupled to the memory. The decimation circuit decimates the sampling rate of received data to produce a decimated rate. The received data is stored in the memory at the decimated rate. The decimated rate is later increased by the interpolation circuit by the interpolation factor when the stored data is retrieved from the memory. The memory is a circular buffer or a single port RAM that is accessible by multiple rake fingers substantially simultaneously via selector circuits.

    METHOD AND APPARATUS FOR TIME-SLICED AND MULTI-THREADED DATA PROCESSING IN A COMMUNICATION SYSTEM
    7.
    发明申请
    METHOD AND APPARATUS FOR TIME-SLICED AND MULTI-THREADED DATA PROCESSING IN A COMMUNICATION SYSTEM 有权
    通信系统中时间多通道数据处理的方法与装置

    公开(公告)号:US20080092141A1

    公开(公告)日:2008-04-17

    申请号:US11841585

    申请日:2007-08-20

    IPC分类号: G06F9/50

    摘要: A method for designing a time-sliced and multi-threaded architecture comprises the steps of conducting a thorough analysis of a range of applications and building a specific processor to accommodate the range of applications. In one embodiment, the thorough analysis includes extracting real time aspects from each application, determining optimal granularity in the architecture based on the real time aspects of each application, and adjusting the optimal granularity based on acceptable context switching overhead.

    摘要翻译: 用于设计时间分割和多线程架构的方法包括以下步骤:对一系列应用进行彻底分析并构建特定处理器以适应应用范围。 在一个实施例中,彻底分析包括从每个应用提取实时方面,基于每个应用的实时方面来确定体系结构中的最佳粒度,以及基于可接受的上下文切换开销来调整最优粒度。

    VIRTUAL MACHINE INTERFACE FOR HARDWARE RECONFIGURABLE AND SOFTWARE PROGRAMMABLE PROCESSORS
    8.
    发明申请
    VIRTUAL MACHINE INTERFACE FOR HARDWARE RECONFIGURABLE AND SOFTWARE PROGRAMMABLE PROCESSORS 有权
    硬件可重构和软件可编程处理器的虚拟机接口

    公开(公告)号:US20080086548A1

    公开(公告)日:2008-04-10

    申请号:US11841848

    申请日:2007-08-20

    IPC分类号: G06F15/177

    CPC分类号: H04L69/18 H04L69/32 H04W88/00

    摘要: The present invention provides a virtual machine interface (VMI) and an application programming interface (API) usable in conjunction with a reconfigurable wireless network communication apparatus. The reconfigurable wireless network communication apparatus comprises a plurality of hardware kernels. The apparatus can be reconfigured to support different or modified communication protocols over time. The VMI comprises a library of software objects. By configuring VMI software objects, a programmer selects the communication protocol used by the reconfigurable wireless network communication apparatus. The API of the present invention provides higher level management of the communication protocol used by a reconfigurable wireless network communication apparatus. The API comprises a library of high level software objects that further abstract hardware details of the apparatus.

    摘要翻译: 本发明提供了一种可配置可重配置的无线网络通信装置的虚拟机接口(VMI)和应用编程接口(API)。 可重配置无线网络通信装置包括多个硬件内核。 该装置可以被重新配置为支持不同或修改的通信协议随着时间的推移。 VMI包括一个软件对象库。 通过配置VMI软件对象,程序员选择可重构无线网络通信设备使用的通信协议。 本发明的API提供了由可重新配置的无线网络通信设备使用的通信协议的更高级别的管理。 该API包括高级软件对象的库,其进一步抽象该装置的硬件细节。

    Signal-to-interference ratio estimation for CDMA
    9.
    发明申请
    Signal-to-interference ratio estimation for CDMA 有权
    CDMA的信号干扰比估计

    公开(公告)号:US20050143117A1

    公开(公告)日:2005-06-30

    申请号:US10750924

    申请日:2003-12-31

    摘要: Calculating of signal-to-interference ratio (SIR) of a mobile device in a wireless communication system. A communication signal transmitted by the mobile device is non-coherently processed. Interference power of the communication signal is estimated and then scaled, and the scaled estimated interference power is subtracted from the processed communication signal to thereby estimate signal power. The SIR is calculated by dividing the estimated signal power by the estimated interference power.

    摘要翻译: 计算无线通信系统中的移动设备的信号干扰比(SIR)。 由移动设备发送的通信信号是非相干处理的。 对通信信号的干扰功率进行估计,然后进行缩放,并从经处理的通信信号中减去经缩放的估计干扰功率,从而估计信号功率。 通过将估计的信号功率除以估计的干扰功率来计算SIR。

    Apparatus and method for calculating and implementing a fibonacci mask for a code generator

    公开(公告)号:US20060109888A1

    公开(公告)日:2006-05-25

    申请号:US11233419

    申请日:2005-09-16

    申请人: Joel Medlock

    发明人: Joel Medlock

    IPC分类号: H04B1/69

    摘要: An apparatus and method for calculating and implementing a Fibonacci mask for a code generator is disclosed herein. The first step receives a desired code offset from a reference code state in a Fibonacci field. Next, a field vector in a Galois field with the same code offset sought in the first field is calculated. In the next step, the first field vector is transformed into a second field vector, which is operable as a mask in the Galois LFSR. The transform step is accomplished by multiplying the Galois field vector by a linear N×N transformation matrix to obtain the Fibonacci field vector. And the N×N transformation matrix is obtained from iterated states of the Fibonacci LFSR.