公开(公告)号：US20060039317A1

公开(公告)日：2006-02-23

申请号：US11200854

申请日：2005-08-09

申请人： Ravi Subramanian ,  Keith Rieken ,  Uma Jha ,  Joel Medlock ,  Christopher Woodthorpe

发明人： Ravi Subramanian ,  Keith Rieken ,  Uma Jha ,  Joel Medlock ,  Christopher Woodthorpe

IPC分类号： H04Q7/00

CPC分类号： H04B1/0007 ,  H04B1/0003 ,  H04B1/406 ,  H04W24/00 ,  H04W28/10 ,  H04W88/08 ,  H04W88/10

摘要： An apparatus for digitally processing signals within wireless communications base-stations which includes a channel pooling signal processor and a digital signal processor. The channel pooling signal processor includes a plurality of computation units typically realized in a heterogeneous multiprocessing architecture, a test interface for testing the function of the plurality of the computation units, a general-purpose microprocessor for managing the dataflow into and out of the channel pooling signal processor as well as effecting the control and configuration of the computation units, and an interconnect mechanism for connecting the plurality of computation units to the input, output, test interface, and the general-purpose microprocessor.

摘要翻译： 一种用于数字处理无线通信基站内的信号的装置，包括信道汇集信号处理器和数字信号处理器。 信道池信号处理器包括通常在异构多处理架构中实现的多个计算单元，用于测试多个计算单元的功能的测试接口，用于管理数据流进出信道池的通用微处理器 信号处理器以及实现计算单元的控制和配置，以及用于将多个计算单元连接到输入，输出，测试接口和通用微处理器的互连机构。

公开(公告)号：US06459883B2

公开(公告)日：2002-10-01

申请号：US09920094

申请日：2001-07-31

申请人： Ravi Subramanian ,  Keith Rieken ,  Uma Jha ,  David M. Holmes ,  Joel D. Medlock ,  Murali Krishnan

发明人： Ravi Subramanian ,  Keith Rieken ,  Uma Jha ,  David M. Holmes ,  Joel D. Medlock ,  Murali Krishnan

IPC分类号： H04B1700

CPC分类号： H04B1/7115 ,  H04B1/7117 ,  H04B2201/7071 ,  H04L2027/0026

摘要： A rake receiver in accordance with an exemplary embodiment of this invention is configurable by an external agent (e.g., microcontroller, DSP, or state machine) to suit the particular requirements of different spread spectrum systems. In an exemplary embodiment, the receiver includes multiple fingers. Each finger includes a plurality of generic despreaders/descramblers, a plurality of generic dechannelizers coupled to the despreaders/descramblers, and at least one timing estimation controller coupled to the despreaders/descramblers. The finger also includes at least one phase estimation controller, at least one frequency estimation controller, and at least one energy estimation controller all coupled to the generic dechannelizers.

摘要翻译： 根据本发明的示例性实施例的耙式接收机可由外部代理（例如，微控制器，DSP或状态机）来配置，以适应不同扩频系统的特定要求。 在示例性实施例中，接收机包括多个指状物。 每个手指包括多个通用去扩展器/解扰器，耦合到解扩器/解扰器的多个通用去通道化器，以及耦合到解扩器/解扰器的至少一个定时估计控制器。 手指还包括至少一个相位估计控制器，至少一个频率估计控制器和至少一个能量估计控制器，所述至少一个能量估计控制器全部耦合到通用去通道分配器。

公开(公告)号：US06967999B2

公开(公告)日：2005-11-22

申请号：US09752050

申请日：2000-12-29

申请人： Ravi Subramanian ,  Keith Rieken ,  Uma Jha ,  Joel D. Medlock ,  Christopher C. Woodthorpe

发明人： Ravi Subramanian ,  Keith Rieken ,  Uma Jha ,  Joel D. Medlock ,  Christopher C. Woodthorpe

IPC分类号： H04B1/40 ,  H04B17/00 ,  H04L12/56 ,  H04L25/00 ,  H04L27/00 ,  H04W24/00 ,  H04W28/10 ,  H04W88/08 ,  H04W88/10

CPC分类号： H04B1/0007 ,  H04B1/0003 ,  H04B1/406 ,  H04W24/00 ,  H04W28/10 ,  H04W88/08 ,  H04W88/10

摘要： An apparatus for digitally processing signals within wireless communications base-stations which includes a channel pooling signal processor and a digital signal processor. The channel pooling signal processor includes a plurality of computation units typically realized in a heterogeneous multiprocessing architecture, a test interface for testing the function of the plurality of the computation units, a general-purpose microprocessor for managing the dataflow into and out of the channel pooling signal processor as well as effecting the control and configuration of the computation units, and an interconnect mechanism for connecting the plurality of computation units to the input, output, test interface, and the general-purpose microprocessor.

摘要翻译： 一种用于数字处理无线通信基站内的信号的装置，包括信道汇集信号处理器和数字信号处理器。 信道池信号处理器包括通常在异构多处理架构中实现的多个计算单元，用于测试多个计算单元的功能的测试接口，用于管理数据流进出信道池的通用微处理器 信号处理器以及实现计算单元的控制和配置，以及用于将多个计算单元连接到输入，输出，测试接口和通用微处理器的互连机构。

公开(公告)号：US20080084850A1

公开(公告)日：2008-04-10

申请号：US11841604

申请日：2007-08-20

申请人： Song Chen ,  Paul Chou ,  Christopher Woodthorpe ,  Venugopal Balasubramonian ,  Keith Rieken

发明人： Song Chen ,  Paul Chou ,  Christopher Woodthorpe ,  Venugopal Balasubramonian ,  Keith Rieken

IPC分类号： H04B7/216 ,  H04J3/06

CPC分类号： G06F15/78 ,  G06F9/30079 ,  G06F9/30083 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3885 ,  G06F9/462 ,  G06F9/4881 ,  Y02D10/24

摘要： A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.

摘要翻译： 无线通信系统根据通信协议承载多个进程。 该系统包括为该过程提供计算支持的特定于应用程序的指令集处理器（ASISP）。 每个ASISP能够执行通信协议的功能的子集。 调度程序用于以时间分片算法调度ASISP，以便每个ASISP支持多个进程。 在这种体系结构中，ASISP在任何给定的时间主动执行一个受支持进程（活动进程）的计算。 由特定ASISP支持的每个进程的状态信息存储在与ASISP唯一相关联的存储体中。 当调度器指示ASISP改变哪个进程是活动进程时，将非活动进程的状态信息存储在存储体中，并且从存储体检索新激活的进程的状态信息。

公开(公告)号：US20080092141A1

公开(公告)日：2008-04-17

申请号：US11841585

申请日：2007-08-20

申请人： Keith Rieken ,  Joel Medlock ,  David Holmes

发明人： Keith Rieken ,  Joel Medlock ,  David Holmes

IPC分类号： G06F9/50

CPC分类号： G06F9/4887 ,  H04B1/707 ,  H04B1/7117 ,  H04B2201/70707 ,  H04B2201/7071

摘要： A method for designing a time-sliced and multi-threaded architecture comprises the steps of conducting a thorough analysis of a range of applications and building a specific processor to accommodate the range of applications. In one embodiment, the thorough analysis includes extracting real time aspects from each application, determining optimal granularity in the architecture based on the real time aspects of each application, and adjusting the optimal granularity based on acceptable context switching overhead.

摘要翻译： 用于设计时间分割和多线程架构的方法包括以下步骤：对一系列应用进行彻底分析并构建特定处理器以适应应用范围。 在一个实施例中，彻底分析包括从每个应用提取实时方面，基于每个应用的实时方面来确定体系结构中的最佳粒度，以及基于可接受的上下文切换开销来调整最优粒度。

公开(公告)号：US20060291542A1

公开(公告)日：2006-12-28

申请号：US11447228

申请日：2006-06-05

申请人： Joel Medlock ,  Keith Rieken ,  David Holmes

发明人： Joel Medlock ,  Keith Rieken ,  David Holmes

IPC分类号： H04B1/00

CPC分类号： H04B1/7117 ,  H04B2201/70707

摘要： An apparatus for reducing storage requirements and for allowing reuse of multiple rake fingers in a spread spectrum system includes a decimation circuit having an associated decimation factor, a memory coupled to the decimation circuit, and an interpolation circuit having an interpolation factor coupled to the memory. The decimation circuit decimates the sampling rate of received data to produce a decimated rate. The received data is stored in the memory at the decimated rate. The decimated rate is later increased by the interpolation circuit by the interpolation factor when the stored data is retrieved from the memory. The memory is a circular buffer or a single port RAM that is accessible by multiple rake fingers substantially simultaneously via selector circuits.

公开(公告)号：US08014786B2

公开(公告)日：2011-09-06

申请号：US11841604

申请日：2007-08-20

申请人： Song Chen ,  Paul L. Chou ,  Christopher C. Woodthorpe ,  Venugopal Balasubramonian ,  Keith Rieken

发明人： Song Chen ,  Paul L. Chou ,  Christopher C. Woodthorpe ,  Venugopal Balasubramonian ,  Keith Rieken

IPC分类号： H04Q7/20

CPC分类号： G06F15/78 ,  G06F9/30079 ,  G06F9/30083 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3885 ,  G06F9/462 ,  G06F9/4881 ,  Y02D10/24

摘要： A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.

摘要翻译： 无线通信系统根据通信协议承载多个进程。 该系统包括为该过程提供计算支持的特定于应用程序的指令集处理器（ASISP）。 每个ASISP能够执行通信协议的功能的子集。 调度程序用于以时间分片算法调度ASISP，以便每个ASISP支持多个进程。 在这种体系结构中，ASISP在任何给定的时间主动执行一个受支持进程（活动进程）的计算。 由特定ASISP支持的每个进程的状态信息存储在与ASISP唯一相关联的存储体中。 当调度器指示ASISP改变哪个进程是活动进程时，将非活动进程的状态信息存储在存储体中，并且从存储体检索新激活的进程的状态信息。

公开(公告)号：US07606576B2

公开(公告)日：2009-10-20

申请号：US09912721

申请日：2001-07-24

申请人： Song Chen ,  Paul L. Chou ,  Christopher C. Woodthorpe ,  Venugopal Balasubramonian ,  Keith Rieken

发明人： Song Chen ,  Paul L. Chou ,  Christopher C. Woodthorpe ,  Venugopal Balasubramonian ,  Keith Rieken

IPC分类号： H04Q7/20

CPC分类号： G06F15/78 ,  G06F9/30079 ,  G06F9/30083 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3885 ,  G06F9/462 ,  G06F9/4881 ,  Y02D10/24

摘要： A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.

公开(公告)号：US07536691B2

公开(公告)日：2009-05-19

申请号：US09927906

申请日：2001-08-09

申请人： Chakki Kavoori ,  Keith Rieken ,  David M. Holmes

发明人： Chakki Kavoori ,  Keith Rieken ,  David M. Holmes

IPC分类号： G06F9/46 ,  G06F15/173

CPC分类号： H04L29/06 ,  G06F9/44521 ,  H04L69/12 ,  H04W72/1215 ,  H04W88/02

摘要： An architecture and method for dynamic resource allocation and scheduling in a communication device is disclosed herein. The method of controlling hardware resources in a communication device having a processor, a computer readable memory, and at least one hardware resource coupled to each other includes several steps. The first step locates a memory address in the computer readable memory that is associated with a first hardware resource. In the next step, control information associated with the first memory address is transmitted to the first hardware resource for it to be operated. In the last step, a pointer associated with the first address that locates a subsequent address for a subsequent hardware resource, is read.

摘要翻译： 本文公开了一种用于通信设备中的动态资源分配和调度的架构和方法。 在具有处理器，计算机可读存储器和至少一个彼此耦合的硬件资源的通信设备中控制硬件资源的方法包括几个步骤。 第一步找到与第一硬件资源相关联的计算机可读存储器中的存储器地址。 在下一步骤中，将与第一存储器地址相关联的控制信息发送到第一硬件资源以供操作。 在最后一步中，读取与定位后续硬件资源的后续地址的第一地址相关联的指针。

公开(公告)号：US07065128B2

公开(公告)日：2006-06-20

申请号：US09920095

申请日：2001-07-31

申请人： Joel D. Medlock ,  Keith Rieken ,  David M. Holmes

发明人： Joel D. Medlock ,  Keith Rieken ,  David M. Holmes

IPC分类号： H04B1/69

CPC分类号： H04B1/7117 ,  H04B2201/70707

摘要： An apparatus for reducing storage requirements and for allowing reuse of multiple rake fingers in a spread spectrum system includes a decimation circuit having an associated decimation factor, a memory coupled to the decimation circuit, and an interpolation circuit having an interpolation factor coupled to the memory. The decimation circuit decimates the sampling rate of received data to produce a decimated rate. The received data is stored in the memory at the decimated rate. The decimated rate is later increased by the interpolation circuit by the interpolation factor when the stored data is retrieved from the memory. The memory is a circular buffer or a single port RAM that is accessible by multiple rake fingers substantially simultaneously via selector circuits.