公开(公告)号：US07573097B2

公开(公告)日：2009-08-11

申请号：US10981175

申请日：2004-11-03

申请人： John C. Desko ,  Roger A. Fratti ,  Vivian Ryan

发明人： John C. Desko ,  Roger A. Fratti ,  Vivian Ryan

IPC分类号： H01L29/417 ,  H01L29/423

CPC分类号： H01L29/7835 ,  H01L23/4824 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The specification describes an improved mechanical electrode structure for MOS transistor devices with elongated runners. It recognizes that shrinking the geometry increases the likelihood of mechanical failure of comb electrode geometries. The mechanical integrity of a comb electrode is improved by interconnecting the electrode fingers in a cross-connected grid. In one embodiment, the transistor device is interconnected with gate fingers on a lower metaliization level, typically the first level metal, with the drain interconnected at a higher metal level. That allows the drain fingers to be cross-connected with a vertical separation between drain and gate comb electrodes. The cross-connect members may be further stabilized by adding beam extensions to the cross-connect members. The beam extensions may be anchored in an interlevel dielectric layer for additional support.

摘要翻译： 本说明书描述了具有细长流道的用于MOS晶体管器件的改进的机械电极结构。 它认识到缩小几何形状增加了梳状电极几何形状的机械故障的可能性。 梳状电极的机械完整性通过将电极指互连在一个交叉连接的网格中来改进。 在一个实施例中，晶体管器件与较低的金属化级别（通常为第一级金属）与栅极指状物互连，漏极互连在较高的金属水平。 这允许漏极指与电极和门梳电极之间的垂直间隔交叉连接。 交叉连接构件可以通过向交叉连接构件添加梁延伸而进一步稳定。 光束延伸部可以锚定在层间电介质层中用于额外的支撑。

公开(公告)号：US06828649B2

公开(公告)日：2004-12-07

申请号：US10140616

申请日：2002-05-07

申请人： John C. Desko ,  Thomas J. Krutsick ,  Chung-Ming Hsieh ,  Brian E. Thompson ,  Bailey Jones ,  Steve Wallace

发明人： John C. Desko ,  Thomas J. Krutsick ,  Chung-Ming Hsieh ,  Brian E. Thompson ,  Bailey Jones ,  Steve Wallace

IPC分类号： H01L2900

CPC分类号： H01L21/763 ,  H01L21/743 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. In one advantageous embodiment, the semiconductor device includes a doped layer located over a semiconductor substrate, and an isolation trench located in the doped layer and having a dielectric layer located on a sidewall thereof. The semiconductor device may further include a conductive material located within the isolation trench and an interconnect that electrically connects the conductive material and the doped layer.

摘要翻译： 本发明提供一种半导体器件及其制造方法以及包括该半导体器件的集成电路。 在一个有利的实施例中，半导体器件包括位于半导体衬底上的掺杂层和位于掺杂层中并且位于其侧壁上的介电层的隔离沟槽。 半导体器件还可以包括位于隔离沟槽内的导电材料和电连接导电材料和掺杂层的互连。