公开(公告)号：US20100052026A1

公开(公告)日：2010-03-04

申请号：US12200538

申请日：2008-08-28

申请人： John Edward Barth, JR. ,  Kerry Bernstein ,  Ethan Harrison Cannon ,  Francis Roger White

发明人： John Edward Barth, JR. ,  Kerry Bernstein ,  Ethan Harrison Cannon ,  Francis Roger White

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10861 ,  H01L29/66181

摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.

摘要翻译： 公开了半导体结构。 半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二 所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。 深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。 半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。

公开(公告)号：US20110199837A1

公开(公告)日：2011-08-18

申请号：US12704703

申请日：2010-02-12

申请人： William Robert Reohr ,  John Edward Barth, JR. ,  Toshiaki Kirihata ,  Derek H. Leu ,  Donald W. Plass

发明人： William Robert Reohr ,  John Edward Barth, JR. ,  Toshiaki Kirihata ,  Derek H. Leu ,  Donald W. Plass

IPC分类号： G11C8/08 ,  G11C7/00

CPC分类号： G11C8/08 ,  G11C11/4085

摘要： A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.

摘要翻译： 耦合到存储器电路字线的字线驱动电路包括上拉，上拉钳位，下拉和下拉钳位晶体管，每个具有源极，漏极和栅极。 对于上拉晶体管，源极耦合到第一电源，并将栅极耦合到上拉控制信号。 对于上拉钳位晶体管，源极耦合到上拉晶体管的漏极，到字线的漏极，并将栅极耦合到上拉钳位信号。 对于下拉晶体管，源极耦合到第二电源，并将栅极耦合到下拉控制信号。 对于下拉钳位晶体管，源极耦合到下拉晶体管的漏极，漏极到字线，而栅极耦合到下拉钳位栅极信号。 字线耦合到一个或多个DRAM单元。 源极到漏极上拉和下拉晶体管的电压幅度小于第一和第二电源之间的电压。

公开(公告)号：US20100054057A1

公开(公告)日：2010-03-04

申请号：US12199438

申请日：2008-08-27

申请人： Mesut Meterelliyoz ,  John Edward Barth, JR. ,  William Robert Reohr

发明人： Mesut Meterelliyoz ,  John Edward Barth, JR. ,  William Robert Reohr

IPC分类号： G11C7/06 ,  G11C7/00

CPC分类号： G11C11/4091 ,  G11C11/4097

摘要： Techniques for sensing data states of respective memory cells in a memory array are provided, the memory array including at least a first bit line coupled to at least a subset of the memory cells. In one aspect, a circuit for sensing data states of respective memory cells in the memory array includes at least one sense amplifier coupled to the first bit line. The sense amplifier includes a first transistor operative to selectively inhibit charging of the first bit line in a manner which is independent of a voltage level on a second bit line coupled to the sense amplifier.

摘要翻译： 提供了用于感测存储器阵列中的相应存储器单元的数据状态的技术，所述存储器阵列至少包括耦合到所述存储器单元的至少一个子集的第一位线。 在一个方面，用于感测存储器阵列中各个存储单元的数据状态的电路包括耦合到第一位线的至少一个读出放大器。 感测放大器包括第一晶体管，其操作以选择性地禁止第一位线的充电，其方式与在与读出放大器耦合的第二位线上的电压电平无关。