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222 条记录 (耗时 0.028 秒)

    Deep trench capacitor for SOI CMOS devices for soft error immunity
    1.
    发明授权
    Deep trench capacitor for SOI CMOS devices for soft error immunity 有权
    用于SOI CMOS器件的深沟槽电容器，用于软误差抗扰度

    公开(公告)号：US07989865B2

    公开(公告)日：2011-08-02

    申请号：US12200538

    申请日：2008-08-28

    申请人： John Edward Barth, Jr. ,  Kerry Bernstein ,  Ethan Harrison Cannon ,  Francis Roger White

    发明人： John Edward Barth, Jr. ,  Kerry Bernstein ,  Ethan Harrison Cannon ,  Francis Roger White

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10861 ,  H01L29/66181

    摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.

    摘要翻译： 公开了半导体结构。 半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二 所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。 深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。 半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。

    DEEP TRENCH CAPACITOR FOR SOI CMOS DEVICES FOR SOFT ERROR IMMUNITY
    2.
    发明申请
    DEEP TRENCH CAPACITOR FOR SOI CMOS DEVICES FOR SOFT ERROR IMMUNITY 有权
    用于软错误免疫的SOI CMOS器件的深度TRENCH电容器

    公开(公告)号：US20100052026A1

    公开(公告)日：2010-03-04

    申请号：US12200538

    申请日：2008-08-28

    申请人： John Edward Barth, JR. ,  Kerry Bernstein ,  Ethan Harrison Cannon ,  Francis Roger White

    发明人： John Edward Barth, JR. ,  Kerry Bernstein ,  Ethan Harrison Cannon ,  Francis Roger White

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10861 ,  H01L29/66181

    摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.

    摘要翻译： 公开了半导体结构。 半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二 所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。 深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。 半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。

    Trench decoupling capacitor formed by RIE lag of through silicon via (TSV) etch
    3.
    发明授权
    Trench decoupling capacitor formed by RIE lag of through silicon via (TSV) etch 失效
    通过硅经过（TSV）蚀刻的RIE滞后形成的沟槽去耦电容器

    公开(公告)号：US08298906B2

    公开(公告)日：2012-10-30

    申请号：US12511545

    申请日：2009-07-29

    申请人： Kerry Bernstein ,  Francis Roger White

    发明人： Kerry Bernstein ,  Francis Roger White

    IPC分类号： H01L21/20

    CPC分类号： H01L21/3065 ,  H01L21/76898 ,  H01L29/66181

    摘要： A trench decoupling capacitor is formed using RIE lag of a through silicon via (TSV) etch. A method includes etching a via trench and a capacitor trench in a wafer in a single RIE process. The via trench has a first depth and the capacitor trench has a second depth less than the first depth due to RIE lag.

    摘要翻译： 使用通过硅通孔（TSV）蚀刻的RIE滞后来形成沟槽去耦电容器。 一种方法包括在单个RIE工艺中蚀刻晶片中的通孔沟槽和电容器沟槽。 通孔沟槽具有第一深度，并且由于RIE滞后，电容器沟槽具有小于第一深度的第二深度。

    Inactivity triggered self clocking logic family
    6.
    发明授权
    Inactivity triggered self clocking logic family 有权
    不活动触发自我计时逻辑家族

    公开(公告)号：US08575964B2

    公开(公告)日：2013-11-05

    申请号：US13426776

    申请日：2012-03-22

    申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  John Sargis, Jr. ,  Sebastian T. Ventrone ,  Charles S. Woodruff

    发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  John Sargis, Jr. ,  Sebastian T. Ventrone ,  Charles S. Woodruff

    IPC分类号： H03K19/00

    CPC分类号： H03K19/0966 ,  H03K19/0013

    摘要： Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.

    摘要翻译： 电路的局部逻辑区域包括电连接到局部电阻电压电路的本地比较器，局部电阻接地电路和局部寄存器结构。 当本地参考电压低于本地电压阈值时，本地比较器会向本地寄存器结构提供时钟脉冲。 本地组合逻辑结构中的活动导致本地参考电压低于局部参考电压，而与全局参考电压的变化无关，导致比较器输出时钟脉冲（具有足够的延迟以允许逻辑结果存储在寄存器中 只有在本地逻辑设备中已经满足设置时间之后）。 这消除了对时钟分配树的需要，从而在局部组合逻辑结构中没有活动时节省功率。

    SEMICONDUCTOR CHIP STACKING FOR REDUNDANCY AND YIELD IMPROVEMENT
    8.
    发明申请
    SEMICONDUCTOR CHIP STACKING FOR REDUNDANCY AND YIELD IMPROVEMENT 有权
    用于冗余和改进的半导体芯片堆叠

    公开(公告)号：US20120326333A1

    公开(公告)日：2012-12-27

    申请号：US13607680

    申请日：2012-09-08

    申请人： Kerry Bernstein ,  Philip G. Emma ,  Michael Ignatowski

    发明人： Kerry Bernstein ,  Philip G. Emma ,  Michael Ignatowski

    IPC分类号： H01L25/00

    CPC分类号： H01L25/0657 ,  H01L25/0652 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality.

    摘要翻译： 包括多个单元芯片的堆叠半导体芯片包含具有低产出并分布在多个单元芯片之间的第一芯片组件的多个实例。 第一单元芯片内的第一芯片组件的实例与至少另一个单元芯片内的第一芯片组件的至少另一个实例进行逻辑配对，使得跨多个单元芯片的第一芯片组件的多个实例的组合构成 提供第一芯片组件的完全功能实例的功能的功能块。 层叠的半导体芯片可以包括具有高产量并分布在多个单元芯片上的第二芯片组件的多个实例。 多个低产量组分构成提供增强的总收率的功能块，而高产量组分被用于其全部潜在功能。

    Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices
    9.
    发明授权
    Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices 失效
    用于绝缘体上硅（SOI）器件的深沟槽静电放电（ESD）保护二极管

    公开(公告)号：US08263472B2

    公开(公告)日：2012-09-11

    申请号：US13324486

    申请日：2011-12-13

    申请人： John E. Barth, Jr. ,  Kerry Bernstein

    发明人： John E. Barth, Jr. ,  Kerry Bernstein

    IPC分类号： H01L21/76

    CPC分类号： H01L29/861 ,  H01L21/761 ,  H01L21/76264 ,  H01L23/535 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.

    摘要翻译： 半导体包括第一极性类型的体基板，设置在体基板上的掩埋绝缘体层，设置在包括浅沟槽隔离区域和第一极性类型的扩散区域的掩埋绝缘体层的顶部上的有源半导体层， 第二极性类型的带区域直接设置在掩埋绝缘体层的正下方并形成导电路径，第二极性类型的阱区域布置在本体衬底中并与带区域接触，填充有导电材料的深沟槽 设置在阱区内的第一极性类型和由深沟槽的下部与阱区之间的接合部限定的静电放电（ESD）保护二极管。

    Soft error correction in sleeping processors
    10.
    发明授权
    Soft error correction in sleeping processors 有权
    睡眠处理器中的软错误校正

    公开(公告)号：US08234554B2

    公开(公告)日：2012-07-31

    申请号：US12170462

    申请日：2008-07-10

    申请人： Kerry Bernstein ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Norman J. Rohrer

    IPC分类号： H03M13/00

    CPC分类号： H03M13/15 ,  G06F11/1008 ,  H03M13/098 ,  H03M13/13 ,  H03M13/1505 ,  H03M13/19

    摘要： An error-correction code is generated on a line-by-line basis of the physical logic register and latch contents that store encoded words within a processor just before the processor is put into sleep mode, and later-generated syndrome bits are checked for any soft errors when the processor wakes back up, e.g., as part of the power-up sequence.

    摘要翻译： 在处理器进入睡眠模式之前，将物理逻辑寄存器和锁存内容逐行生成在处理器内的处理器内，生成错误校正码，并检查后来生成的校验码位 处理器唤醒时出现软错误，例如作为上电顺序的一部分。